CS5530A datasheet(63/259 Pages) NSC

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Functional Description (Continued)

3.4.3

Peripheral Power Management

The CS5530A provides peripheral power management

using a combination of device idle timers, address traps,

and general purpose I/O pins. Idle timers are used in con-

junction with traps to support powering down peripheral

devices. Eight programmable GPIO (general purpose I/O)

pins are included for external device power control as well

as other functions. All I/O addresses are decoded in 16

bits. All memory addresses are decoded in 32 bits.

3.4.3.1

Device Idle Timers and Traps

Idle timers are used to power manage a peripheral by

determining when the peripheral has been inactive for a

specified period of time, and removing power from the

peripheral at the end of that time period.

Idle timers are provided for the commonly-used peripherals

(FDC, IDE, parallel/serial ports, and mouse/keyboard). In

addition, there are three user-defined timers that can be

configured for either I/O or memory ranges. The Power

Management enable bit (F0 Index 80h[1]) enables and dis-

ables the power management idle timers. The Trap bit in

the same register (F0 Index 80h[2]) enables and disables

device I/O traps.

Theidletimersare 16-bitcountdowntimers witha1 sec-

ond time base, providing a time-out range of 1 to 65536

seconds (1092 minutes) (18 hours). General purpose tim-

ers can be programmed to count milliseconds instead of

seconds (see Section 3.4.3.2 on page 73 for further infor-

mation on general purpose timers).

When the idle timers are enabled, the timers are loaded

from the timer count registers and start to decrement at the

next timebase clock, but cannot trigger an interrupt on that

cycle. If an idle timer is initially set to 1, it decrements to 0

on the first cycle and continues counting with 65535 on the

next cycle. Starting at 2 gives 1 on the first cycle, and 0 on

the second cycle, generating the interrupt. Since the time-

base is one second, the minimum interval before the next

interrupt from this timer is variable, from one to two sec-

onds with a setting of two.

The idle timers continue to decrement until one of two pos-

sibilities occurs: a bus cycle occurs at that I/O or memory

range, or the timer decrements to zero.

When abus cycleoccurs, the idletimer is reloadedwithits

starting value. It then continues to decrement.

When the timer decrements to zero, if power management

is enabled (F0 Index 80h[0] = 1), the timer generates an

SMI. (F0 Index 80h[0] = 0 does not disable these timers

from running, but only from generating SMI.)

When an idle timer generates an SMI, the SMI handler

manages the peripheral power, disables the timer, and

enables the trap. The next time an event occurs, the trap

generates an SMI. This time, the SMI handler applies

power to the peripheral, enables the timer (thus reloading

its starting value), and disables the trap.

Tables 3-17 through 3-25 show the device associated idle

timers and traps programming bits.

Table 3-17. Power Management Global Enabling Bits

Bit

Description

F0 Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx)

Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0

Index AEh).

Power Management: Global power management. 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the

command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for

F0 Index 84h-87h are disabled. A ‘0’ in this bit does NOT stop the Idle Timers if bit 1 of this register is a ‘1’, but only prevents

them from generating an SMI# interrupt. It also has no effect on the UDEF traps.

CS5530A Datasheet(PDF) 63 Page - National Semiconductor (TI)

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