CS5530A datasheet(97/259 Pages) NSC

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Functional Description (Continued)

The middle address portion, which selects a block within

the page, is generated by the DMA controller at the begin-

ning of a DMA operation and any time the DMA address

increments or decrements through a block boundary. Block

sizes are 256 bytes for 8-bit channels (Channels 0 through

3) and 512 bytes for 16-bit channels (Channels 5, 6, and

7). The middle address bits are driven on PCI address bits

AD[15:8] for 8-bit channels and AD[16:9] for 16-bit chan-

nels.

The lower address portion is generated directly by the DMA

controller during DMA operations. The lower address bits

are output on PCI address bits AD[7:0] for 8-bit channels

and AD[8:1] for 16-bit channels.

SBHE# is configured as an output during all DMA opera-

tions. It is driven as the inversion of AD0 during 8-bit DMA

cycles and forced low for all 16-bit DMA cycles.

3.5.4.2

Programmable Interval Timer

The CS5530A contains an 8254-equivalent Programmable

Interval Timer (PIT) configured as shown in Figure 3-14.

The PIT has three timers/counters, each with an input fre-

quency of 1.19318 MHz (OSC divided by 12), and individu-

ally programmable to different modes.

The gates of Counter 0 and 1 are usually enabled, how-

ever, they can be controlled via F0 Index 50h (see Table 3-

41). The gate of Counter 2 is connected to I/O Port

061h[0]. The output of Counter 0 is connected internally to

IRQ0. This timer is typically configured in Mode 3 (square

wave output), and used to generate IRQ0 at a periodic rate

to be used as a system timer function. The output of

Counter 1 is connected to I/O Port 061h[4]. The reset state

of I/O Port 061h[4] is 0 and every falling edge of Counter 1

output causes I/O Port 061h[4] to flip states. The output of

Counter 2 is brought out to the PC_BEEP output. This out-

put is gated with I/O Port 061h[1].

Figure 3-14. PIT Timer

Table 3-41. PIT Control and I/O Port 061h Associated Register Bits

Bit

Description

F0 Index 50h

PIT Control/ISA CLK Divider (R/W)

Reset Value = 7Bh

PIT Software Reset: 0 = Disable; 1 = Enable.

PIT Counter 1: 0 = Forces Counter 1 output (OUT1) to zero; 1 = Allows Counter 1 output (OUT1) to pass to I/O

Port 061h[4].

PIT Counter 1 Enable: 0 = Sets GATE1 input low; 1 = Sets GATE1 input high.

PIT Counter 0: 0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0.

PIT Counter 0 Enable: 0 = Sets GATE0 input low; 1 = Sets GATE0 input high.

I/O Port 061h

Port B Control Register (R/W)

Reset Value = 00x01100b

PIT OUT2 State (Read Only): This bit reflects the current status of the PIT Counter 2 (OUT2).

Toggle (Read Only): This bit toggles on every falling edge of Counter 1 (OUT1).

PIT Counter2 (SPKR): 0 = Forces Counter 2 output (OUT2) to zero; 1 = Allows Counter 2 output (OUT2) to pass to the

speaker.

PIT Counter2 Enable: 0 = Sets GATE2 input low; 1 = Sets GATE2 input high.

CLK0

CLK1

CLK2

GATE0

GATE1

GATE2

XD[7:0]

A[1:0]

IOW#

IOR#

I/O Port 061h[1]

I/O Port 061h[0]

IRQ0

I/O Port 061h[4]

PC_BEEP

1.19318 MHz

WR#

RD#

OUT0

OUT1

OUT2

F0 Index 50h[4]

F0 Index 50h[6]

F0 Index 50h[3]

F0 Index 50h[5]

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