CS5530A datasheet(7/259 Pages) NSC

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1.0

Architecture Overview

The Geode CS5530A can be described as providing the

functional blocks shown in Figure 1-1.

• PCI bus master/slave interface

• ISA bus interface

• AT compatibility logic

• IDE controllers

• Power management

—GPIO interfaces

— Traps, Events, Timers

• Joystick/Game Port interface

• Virtual audio support hardware

• Video display, which includes MPEG accelerator,

RAMDAC, and video ports

• USB controller

For CPU interface connection refer to Figure 1-5 "Example

System Block Diagram" on page 12.

1.1

PCI BUS INTERFACE

The CS5530A provides a PCI bus interface that is both a

slave for PCI cycles initiated by the CPU or other PCI mas-

ter devices, and a non-preemptable master for DMA trans-

fer cycles. The chip also is a standard PCI master for the

IDE controllers and audio I/O logic. The CS5530A supports

positive decode for configurable memory and I/O regions

and implements a subtractive decode option for unclaimed

PCI accesses. The CS5530A also generates address and

data parity and performs parity checking. The CS5530A

does not include the PCI bus arbiter, which is located in the

processor.

Configuration registers are accessed through the PCI inter-

face using the PCI Bus Type 1 configuration mechanism as

described in the PCI 2.1 Specification.

Figure 1-1. Internal Block Diagram

X-Bus

ISA Bus

PCI Bus

USB

PCI to X-Bus / X-Bus to PCI Bridge

PCI to USB Macro

Active Decode

Address Mapper

Audio/Codec/MPU

Interface

Pwr Mgmt, Traps,

Events, and Timers

IDE

Interface

Display Interface

MPEG, DOT Clock

CSC and SCL

RGB/FP Interface

AT Compatibility Logic

ISA Bus Interface

AT Ports, ISA Megacells

Display

PCI Configuration

Registers

Graphics

and Video

from CPU

X-Bus Arbiter

CS5530A Support

GPIOs

IDE

AC97 Codec

Ultra DMA/33

(e.g., LM4548)

Joystick / Game Port

Joystick

PC97317 SIO

GPCS

Geode™ CS9211

Graphics Companion

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