CS5530A datasheet(111/259 Pages) NSC

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Functional Description (Continued)

3.6.2.2

Bus Master Mode

Two IDE bus masters are provided to perform the data

transfers for the primary and secondary channels. The

CS5530A off-loads the CPU and improves system perfor-

mance in multitasking environments.

The bus master mode programming interface is an exten-

sion of the standard IDE programming model. This means

that devices can always be dealt with using the standard

IDE programming model, with the master mode functional-

ity used when the appropriate driver and devices are

present. Master operation is designed to work with any IDE

device that supports DMA transfers on the IDE bus.

Devices that work in PIO mode can only use the standard

IDE programming model.

The IDE bus masters use a simple scatter/gather mecha-

nism allowing large transfer blocks to be scattered to or

gathered from memory. This cuts down on the number of

interrupts to and interactions with the CPU.

Physical Region Descriptor Table Address

Before the controller starts a master transfer it is given a

pointer (shown in Table 3-57) to a Physical Region

Descriptor Table. This pointer sets the starting memory

location of the Physical Region Descriptors (PRDs). The

PRDs describe the areas of memory that are used in the

data transfer. The PRDs must be aligned on a 4-byte

boundary and the table cannot cross a 64 KB boundary in

memory.

Primary and Secondary IDE Bus Master Registers

The IDE Bus Master Registers for each channel (primary

and secondary) have an IDE Bus Master Command Regis-

ter and Bus Master Status Register. These registers must

be accessed individually; a 32-bit DWORD access attempt-

ing to include both the Command and Status registers may

not operate correctly. Bit formats of these registers are

giveninTable 3-58.

Table 3-57. IDE Bus Master PRD Table Address Registers

Bit

Description

F2BAR+I/O Offset 04h-07h

IDE Bus Master 0 PRD Table Address — Primary (R/W)

Reset Value = 00000000h

31:2

Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 0.

When written, this register points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit

0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.

When read, this register points to the next PRD.

1:0

Reserved: Set to 0.

F2BAR+I/O Offset 0Ch-0Fh

IDE Bus Master 1 PRD Table Address — Secondary (R/W)

Reset Value = 00000000h

31:2

Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 1.

When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit

0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.

When read, this register points to the next PRD.

1:0

Reserved: Set to 0.

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