DRV10975ZPWPR datasheet(37/65 Pages) TI1

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Motor phase

driving voltage

Fgcycle '00'

4 pole

Fgcycle '01'

6 pole

Fgcycle '10'

8 pole

Fgcycle '11'

12 pole

DRV10975, DRV10975Z

www.ti.com

SLVSCP2E – JANUARY 2015 – REVISED MAY 2018

Product Folder Links: DRV10975

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AVSMMd = 1 – AVS mode becomes active when VCC reaches 24 V. The motor acts as a generator and

returns energy into the power supply until VCC reaches 24 V. This mode can be used to enable faster

deceleration of the motor in applications where returning energy to the power supply is allowed.

8.4.9 PWM Output

The DRV10975 has 16 options for PWM dead time which can be used to configure the time between one of the

bridge FETs turning off and the complementary FET turning on. Deadtime[3:0] can be used to configure dead

times between 40 ns and 640 ns. Take care that the dead time is long enough to prevent the bridge FETs from

shooting through. The recommend minimum dead time is 400 ns for 24-V VCC and 360 ns for 12-V VCC.

The DRV10975 offers two options for PWM switching frequency. When the configuration bit DoubleFreq is set to

0, the output PWM frequency will be 25 kHz and when DoubleFreq is set to 1, the output PWM frequency will be

50 kHz.

8.4.10 FG Customized Configuration

The DRV10975 provides information about the motor speed through the frequency generate (FG) pin. FG also

provides information about the driving state of the DRV10975.

8.4.10.1 FG Output Frequency

The FG output frequency can be configured by FGcycle[1:0]. The default FG toggles once every electrical cycle

(FGcycle = 00). Many applications configure the FG output so that it provides two pulses for every mechanical

rotation of the motor. The configuration bits provided in DRV10975 can accomplish this for 4-pole, 6-pole, 8-pole,

and 12-pole motors, as shown in Figure 35.

Figure 35 shows the DRV10975 has been configured to provide FG pulses once every electrical cycle (4 pole),

twice every three electrical cycle (6 pole), once every two electrical cycles (8 pole), and once every three

electrical cycles (12 pole).

Note that when it is set to 2 FG pulses every three electrical cycles, the FG output is not 50% duty cycle. Motor

speed is able to be measured by monitoring the rising edge of the FG output.

Figure 35. FG Frequency Divider

DRV10975ZPWPR Datasheet(PDF) 37 Page - Texas Instruments