TPS25940 datasheet(21/50 Pages) TI1

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(OUT)

(IN)

(OUT)

- (R

× I

)

(IMON)

(OUT)

(IMON)

(IMON_OS)

(IMON)

= I

x GAIN

x R

(IN)

(IMONmax)

(LIM)

(IMON)

- 2.2, 6)

x GAIN

minimum (V

1.6 x I

TPS25940-Q1

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SLVSDJ0C – MAY 2016 – REVISED JULY 2018

Product Folder Links: TPS25940-Q1

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Feature Description (continued)

8.3.6 Current Monitoring

The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This

current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage,

computed using Equation 6, can be used as a means of monitoring current flow through the system.

The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN) – 2.2 V], 6 V) to

ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 5.

(5)

The output voltage at IMON terminal is calculated from Equation 6.

where

•

GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A

•

I(OUT) = Load current

•

I(IMON_OS) = 0.8 µA (typical)

(6)

This pin must not have a bypass capacitor to avoid delay in the current monitoring information.

The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current

monitor information over an I2C bus.

8.3.7 Power Good Comparator

The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters

or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal

and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator

output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units.

PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal

reference V(PGTHR).

The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy

load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7.

tPGOOD(degl) = Maximum{(3.5 x 10

6 x C

(dVdT)), tPGOODR}

(7)

Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied

to ground when not used.

8.3.8 IN, OUT and GND Pins

The device has multiple pins for input (IN) and output (OUT).

All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device

from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is

2.7 V – 18 V.

Similarly all OUT pins must be connected together and to the load. V(OUT) in the ON condition, is calculated using

Equation 8.

(8)

where, RON is the total ON resistance of the internal FET.

GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference

unless otherwise specified.

8.3.9 Thermal Shutdown

Internal over temperature shutdown disables turns off the FET when TJ > 160°C (typical). The TPS25940L-Q1

version stays latched off, whereas TPS25940-Q1 commences an auto-retry cycle128 ms after TJ drops below

[T(TSD) – 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.

TPS25940 Datasheet(PDF) 21 Page - Texas Instruments

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