TPS25940 datasheet(5/50 Pages) TI1

5 / 50 page

TPS25940-Q1

www.ti.com

SLVSDJ0C – MAY 2016 – REVISED JULY 2018

Product Folder Links: TPS25940-Q1

Submit Documentation Feedback

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

TPS25940x-Q1

UNIT

RVC (WQFN)

20 PINS

RθJA

Junction-to-ambient thermal resistance

38.1

°C/W

RθJCtop

Junction-to-case (top) thermal resistance

40.5

°C/W

RθJB

Junction-to-board thermal resistance

13.6

°C/W

ψJT

Junction-to-top characterization parameter

0.6

°C/W

ψJB

Junction-to-board characterization parameter

13.7

°C/W

RθJCbot

Junction-to-case (bottom) thermal resistance

3.4

°C/W

(1)

These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

6.5 Electrical Characteristics

–40°C

≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1

µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT

V(IN)

Operating input voltage

2.7

V(UVR)

Internal UVLO threshold, rising

2.2

2.3

2.4

V(UVRhys)

Internal UVLO hysteresis

105

116

125

IQ(ON)

Supply current, enabled

V(EN/UVLO) = 2 V, V(IN) = 3 V

140

210

300

µA

V(EN/UVLO) = 2 V, V(IN) = 12 V

140

199

260

V(EN/UVLO) = 2 V, V(IN) = 18 V

140

202

270

IQ(OFF)

Supply current, disabled

V(EN/UVLO) = 0 V, V(IN) = 3 V

8.6

µA

V(EN/UVLO) = 0 V, V(IN) = 12 V

V(EN/UVLO) = 0 V, V(IN) = 18 V

18.5

IQ(DEVSLP)

Supply current, devSleep mode

V(DEVSLP) = 0 V, V(IN) = 2.7 V to 18 V

130

µA

ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT

V(ENR)

EN/UVLO threshold voltage, rising

0.97

0.99

1.01

V(ENF)

EN/UVLO threshold voltage, falling

0.9

0.92

0.94

V(SHUTF)

EN threshold voltage for Low IQ

shutdown, falling

0.3

0.47

0.63

V(SHUTFhys)

EN hysteresis for low IQ shutdown,

hysteresis(1)

IEN

EN Input leakage current

0 V

≤ V(EN/UVLO) ≤ 18 V

–100

100

OVER VOLTAGE PROTECTION (OVP) INPUT

V(OVPR)

Overvoltage threshold voltage, rising

0.97

0.99

1.01

V(OVPF)

Overvoltage threshold voltage,

falling

0.9

0.92

0.94

I(OVP)

OVP input leakage current

0 V

≤ V(OVP) ≤ 5 V

–100

100

DEVSLP MODE INPUT (DEVSLP): ACTIVE HIGH

V(DEVSLPR)

DEVSLP threshold voltage, rising

1.6

1.85

V(DEVSLPF)

DEVSLP threshold voltage, falling

0.8

0.96

1.1

I(DEVSLP)

DEVSLP input leakage current

0.2 V

≤ V(DEVSLP) ≤ 18 V

0.6

1.25

µA

OUTPUT RAMP CONTROL (dVdT)

I(dVdT)

dVdT charging current

V(dVdT) = 0 V

0.85

1.15

µA

R(dVdT)

dVdT discharging resistance

EN/UVLO = 0 V, I(dVdT) = 10 mA sinking

V(dVdTmax)

dVdT maximum capacitor voltage

2.6

2.88

3.1

GAIN(dVdT)

dVdT to OUT gain

ΔV(OUT)/ΔV(dVdT)

11.65

11.9

12.05

V/V

CURRENT LIMIT PROGRAMMING (ILIM)

TPS25940 Datasheet(PDF) 5 Page - Texas Instruments

TPS25940 Datasheet(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL