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DLPC6421 Datasheet(PDF) 19 Page - Texas Instruments |
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DLPC6421 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 48 page  19 DLPC6421 www.ti.com DLPS117 – JULY 2018 Product Folder Links: DLPC6421 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements Parameter MIN MAX UNIT fclock Clock frequency, TCK 10 MHZ t C Cycle time, TCK 100 ns tW(H) Pulse duration, high 50% to 50% reference points (signal) 40 ns tW(L) Pulse duration, low 50% to 50% reference points (signal) 40 ns tt Transition time, tt= tf/tr 20% to 80% reference points (signal) 5 ns tSU Setup time, TDI valid before TCK ↑ 8 ns th Hold time, TDI valid after TCK ↑ 2 ns tSU Setup time, TMS1 valid before TCK ↑ 8 ns th Hold time, TMS1 valid before TCK ↑ 2 ns (1) For frequencies (fclock) less than 175 MHZ, use following formula to obtain the jitter: Max Clock Jitter = +/- [(1/ƒclock) – 5414 ps] (2) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are Asynchronous signals. 6.9 Port 1 Input Pixel Timing Requirements Parameter TEST CONDITIONS MIN MAX UNIT fclock Clock frequency, P_CLK1, P_CLK2, P_CLK3 (30-bit bus) 12 175 MHz fclock Clock frequency, P_CLK1, P_CLK2, P_CLK3 (60-bit bus) 12 160 MHz tC Cycle Time, P_CLK1, P_CLK2, P_CLK3 5.714 83.33 ns tW(H) Pulse Duration, high 50% to 50% reference points (signal) 2.3 ns tW(L) Pulse Duration, low 50% to 50% reference points (signal) 2.3 ns tjp Clock period jitter, P_CLK1, P_CLK2, P_CLK3 Max ƒclock See (1) ps tt Transition time, tt=tf/tr, P_CLK1, P_CLK2, P_CLK3 20% to 80% reference points (signal) 0.6 2.0 ns tt Transition time, tt=tf/tr, P1_A(9-0), P1_B(9-0), P1_C(9-0), P1_HSYNC, P1_VSYNC, P1_DATAEN 20% to 80% reference points (signal) 0.6 3.0 ns tt Transition time, tt=tf/tr, ALF_HSYNC, ALF_VSYNC, ALF_CSYNC(2) 20% to 80% reference points (signal) 0.6 3.0 ns SETUP AND HOLD TIMES tsu Setup time, P1_A(9-0), valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns th Hold time, P1_A(9-0), valid before P_CLK1 ↑↓, P_CLK2↑↓, or P_CLK3 ↑↓ 0.8 ns tsu Setup time, P1_B(9-0), valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns th Hold time, P1_B(9-0), valid before P_CLK1 ↑↓, P_CLK2↑↓, or P_CLK3 ↑↓ 0.8 ns tsu Setup time, P1_C(9-0), valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns th Hold time, P1_C(9-0), valid before P_CLK1 ↑↓, P_CLK2↑↓, or P_CLK3 ↑↓ 0.8 ns tsu Setup time, P1_VSYNC, valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns th Hold time, P1_VSYNC valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns tsu Setup time, P1_HSYNC, valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns th Hold time, P1_HSYNC valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns tsu Setup time, P2_A(9-0), valid before P_CLK1 ↑↓, P_CLK2 ↑↓, or P_CLK3↑↓ 0.8 ns |
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