DLPC6421 datasheet(22/48 Pages) TI1

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DLPC6421

DLPS117 – JULY 2018

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(1)

The frequency of OCLKA thru OCLKC is programmable.

(2)

The Duty Cycle of OCLKA thru OCLKC will be within +/- 2 ns of 50%.

6.12 Programmable Output Clocks Switching Characteristics

Over operating free air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TO (OUTPUT)

MIN

MAX

UNIT

fclock

Clock frequency, OCLKA(1)

OCLKA

0.787

MHz

Cycle Time, OCLKA

OCLKA

1270.6

tW(H)

Pulse Duration, high(2)

50% to 50% reference points

(signal)

OCLKA

(tC/2)-2

tW(L)

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKA

(tC/2)-2

Jitter OCLKA

OCLKA

350

fclock

Clock frequency, OCLKB(1)

OCLKB

0.787

MHz

Cycle Time, OCLKB

OCLKB

1270.6

tW(H)

Pulse Duration, high(2)

50% to 50% reference points

(signal)

OCLKB

(tC/2)-2

tW(L)

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKB

(tC/2)-2

Jitter OCLKB

OCLKB

350

fclock

Clock frequency, OCLKC(1)

OCLKC

0.787

MHz

Cycle Time, OCLKC(2)

OCLKC

1270.6

tW(H)

Pulse Duration, high

50% to 50% reference points

(signal)

OCLKC

(tC/2)-2

tW(L)

Pulse Duration, low(2)

50% to 50% reference points

(signal)

OCLKC

(tC/2)-2

Jitter OCLKC

OCLKC

350

(1)

The SSP can be used as an SSP Master, or as an SSP Slave. When used as a Master, the SSP can be configured to sample DI with

the same internal clock edge used to transmit the next DO. This essentially provides a full cycle rather than a half cycle timing path,

allowing operation at higher SPI clock frequencies.

(2)

The SSP can be configured into four different operational modes/configurations.

6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics

Over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)

PARAMETER

TEST CONDITIONS

FROM (INPUT)

TO (OUTPUT)

MIN

MAX

UNIT

fclock

Clock Frequency,

SSPx_CLK

N/A

SSPx_CLK

25000

kHz

Cycle time, SSPx_CLK

N/A

SSPx_CLK

0.040

13.6

µs

tW(H)

Pulse Duration, high

50% to 50% reference

points (signal)

N/A

SSPx_CLK

40%

tW(L)

Pulse Duration, low

50% to 50% reference

points (signal)

N/A

SSPx_CLK

40%

SSP Master(1)

tpd

Output Propagation,

Clock to Q, SSPx_DO(2)

SSPx_CLK

↓

SSPx_DO

-5

tpd

Output Propagation,

Clock to Q, SSPx_DO(2)

SSPx_CLK

↑

SSPx_DO

-5

SSP Slave(1)

tpd

Output Propagation,

Clock to Q, SSPx_DO(2)

SSPx_CLK

↓

SSPx_DO

tpd

Output Propagation,

Clock to Q, SSPx_DO(2)

SSPx_CLK

↑

SSPx_DO

DLPC6421 Datasheet(PDF) 22 Page - Texas Instruments

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