DLPC6421 datasheet(37/48 Pages) TI1

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DLPC6421

www.ti.com

DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Layout Guidelines (continued)

High frequency decoupling is required for both 1.1-V and 1.8-V PLL supplies and should be provided as close as

possible to each of the PLL supply package pins. TI recommends placing decoupling capacitors under the

package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors.

Typically 0.1µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic

inductance of the mounting and thus, where possible, there should be no trace, allowing the via to butt up

against the land itself. Additionally, the connecting trace should be made as wide as possible. Further

improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.

The location of bulk decoupling depends on the system design.

10.1.2 DMD Interface Considerations

High speed interface waveform quality and timing on the DLPC6421 device (i.e. the LVDS DMD interface) is

dependent on the total length of the interconnect system, the spacing between traces, the characteristic

impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive

timing margin requires attention to many factors.

As an example, DMD Interface system timing margin can be calculated as follows:

•

Setup Margin = (DLPC6421 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI

degradation)

•

Hold-time Margin = (DLPC6421 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI

degradation)

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously

switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The DLPC6421 device I/O

timing parameters as well as DMD I/O timing parameters can be easily found in their corresponding datasheets.

Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI

degradation is not so straight forward.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these

recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements

PDB Design:

● Configuration

Asymmetric Dual Stripline

● Etch Thickness

1.0 oz copper (1.2 mil)

● Flex Etch Thickness

0.5 oz copper (0.6 mil)

● Single Ended Signal Impedance

50 ohms (+/- 10%)

● Differential Signal Impedance

100 ohms differential (+/- 10%)

PCB Stackup:

● Reference plane 1 is assumed to be a ground plane for

proper return path

● Reference plane 2 is assumed to be the I/O power plane

or ground

● Dielectric FR4, (Er):

4.2 (nominal)

● Signal trace distance to reference plane 1 (H1)

5.0 mil (nominal)

● Signal trace distance to reference plane 2 (H2)

34.2 mil (nominal)

DLPC6421 Datasheet(PDF) 37 Page - Texas Instruments

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