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DLPC6421 Datasheet(PDF) 20 Page - Texas Instruments

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Part # DLPC6421
Description  DLP Display Controller
PDF  48 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC6421 Datasheet(HTML) 20 Page - Texas Instruments

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DLPC6421
DLPS117 – JULY 2018
www.ti.com
Product Folder Links: DLPC6421
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Port 1 Input Pixel Timing Requirements (continued)
Parameter
TEST CONDITIONS
MIN
MAX
UNIT
th
Hold time, P2_A(9-0), valid before P_CLK1
↑↓, P_CLK2↑↓,
or P_CLK3
↑↓
0.8
ns
tsu
Setup time, P2_B(9-0), valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P2_B(9-0), valid before P_CLK1
↑↓, P_CLK2↑↓,
or P_CLK3
↑↓
0.8
ns
tsu
Setup time, P2_C(9-0), valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P2_C(9-0), valid before P_CLK1
↑↓, P_CLK2↑↓,
or P_CLK3
↑↓
0.8
ns
tsu
Setup time, P2_VSYNC, valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P2_VSYNC valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
tsu
Setup time, P2_HSYNC, valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P2_HSYNC valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
tsu
Setup time, P_DATAEN1, valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P_DATAEN1 valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
tsu
Setup time, P_DATAEN2, valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
th
Hold time, P_DATAEN2 valid before P_CLK1
↑↓,
P_CLK2
↑↓, or P_CLK3↑↓
0.8
ns
tw(A)
VSYNC Active Pulse Width
1
Video Line
tw(A)
HSYNC Active Pulse Width
16
Pixel
Clocks



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