DLPC6421 datasheet(23/48 Pages) TI1

23 / 48 page

Power Down

PWRGOOD

POSENSE

tt2

80%

50%

20%

tt1

tPH

tw2(L)

DC Power Supplies

80%

50%

20%

tt2

80%

50%

20%

tEW

Power Up

80%

50%

20%

PWRGOOD

tt1

POSENSE

80%

50%

20%

DC Power Supplies

tt1

80%

50%

20%

tw1(L)

tt2

*PWRGOOD has no impact on operation for 60 ms after rising edge of POSENSE.

80%

50%

20%

MOSC

50%

80%

20%

50%

tw(H)

tw(L)

80%

20%

DLPC6421

www.ti.com

DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Table 2. SSP Clock Operational Modes

SPI Clocking Mode

SPI Clock Polarity (CPOL)

SPI Clock Phase (CPHA)

6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics

Over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 85 pF (unless otherwise noted)

PARAMETER

FROM INPUT

TO OUTPUT

MIN

MAX

UNIT

tpd

Output Propagation, Clock to Q

TCK

↓

TDO1

Figure 1. System Oscillators

Figure 2. Power Up

Figure 3. Power Down

DLPC6421 Datasheet(PDF) 23 Page - Texas Instruments

DLPC6421 Datasheet(HTML) 23 Page - Texas Instruments

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