DLPC6421 datasheet(11/48 Pages) TI1

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DLPC6421

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DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Pin Configurations and Functions (continued)

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

GPIO_13

C21

N/A

I2C_2 SDA (B)

GPIO_12

B22

N/A

I2C_2 SCL (B)

GPIO_11

A23

N/A

GPIO_10

A22

N/A

GPIO_9

B21

N/A

GPIO_8

A21

N/A

GPIO_7

A20

N/A

GPIO_6

C20

N/A

GPIO_5

B20

N/A

GPIO_4

B19

N/A

GPIO_3

A19

N/A

GPIO_2

E18

N/A

GPIO_1

D19

N/A

GPIO_0

C19

N/A

CLOCK and PLL SUPPORT

MOSC

M26

I10

System clock oscillator input (3.3-V LVTTL). Note that MOSC must be stable a

maximum of 25ms after POSENSE transitions from low to high.

MOSCN

N26

O10

MOSC crystal return

OCLKA

AF6

General purpose output clock A.

DUAL CONTROLLER SUPPORT

SEQ_SYNC

AB9

Sequence Sync. This signal is used in multi controller configurations only, in which

case the SEQSYNC signal from each controller should be connected together with

an external pull-up. This signal should either be pulled high or pulled low and not

allowed to float for single controller configurations.

POWER and GROUND

VDD33

F20, F17, F11, F8, L21, R21,

Y21, AA19, AA16, AA10, AA7

POWER

3.3-V I/O Power

VDD18

C1, F5, G6, K6, M5, P5, T5,

W6, AA5, AE1, H5, N6, T6,

AA13, U21, P21, H21, F14

POWER

1.8-V Internal DRAM & LVDS I/O Power

VDD11

F19, F16, F13, F10, F7, H6,

L6, P6, U6, Y6, AA8, AA11,

AA14, AA17, AA20, W21, T21,

N21, K21, G21, L11, T11, T16,

L16

POWER

1.1-V Core Power

VDD_PLLD

L22

POWER

1.1-V DMD clock generator PLL digital power

VSS_PLLD

L23

GROUND

1.1-V DMD clock generator PLL digital ground

VAD_PLLD

K25

POWER

1.8-V DMD clock generator PLL analog power

VAS_PLLD

K26

GROUND

1.8-V DMD clock generator PLL analog ground

VDD_PLLM1

L26

POWER

1.1-V Master-LS clock generator PLL digital power

VSS_PLLM1

M22

GROUND

1.1-V Master-LS clock generator PLL digital ground

VAD_PLLM1

L24

POWER

1.8-V Master-LS clock generator PLL analog power

VAS_PLLM1

L25

GROUND

1.8-V Master-LS clock generator PLL analog ground

VDD_PLLM2

P23

POWER

1.1-V Master-HS clock generator PLL digital power

VSS_PLLM2

P24

GROUND

1.1-V Master-HS clock generator PLL digital ground

VAD_PLLM2

R25

POWER

1.8-V Master-HS clock generator PLL analog power

VAS_PLLM2

R26

GROUND

1.8-V Master-HS clock generator PLL analog ground

VAD_PLLS

R23

POWER

1.1-V video-2X clock generator PLL analog power

VAS_PLLS

R24

GROUND

1.1-V video-2X clock generator PLL analog ground

L-VDQPAD_[7:0], R-

VDQPAD_[7:0]

B18, D18, B17, E17, A18, C18,

A17, D17, AE17, AC17, AF17,

AC18, AB16, AD17, AB17,

AD18

RESERVED

These should be tied directly to ground for normal operation.

CFO_VDD33

AE26

RESERVED

This should be tied directly to 3.3 I/O power (VDD33) for normal operation.

VTEST1, VTEST2, VTEST3,

VTEST4

AB14, AB15, E15, E16

RESERVED

These should be tied directly to ground for normal operation.

LVDS_AVS1, LVDS_AVS2

V5, K5

POWER

These should be tied directly to ground for normal operation.

VPGM

AC6

POWER

This should be tied directly to ground for normal operation.

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