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DLPC6421 Datasheet(PDF) 31 Page - Texas Instruments |
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DLPC6421 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 48 page  JTAG HBT SPI I2C 23 16 DATA ADDR 23 16 DATA ADDR 2xLVDS East (960x1080 @240Hz) 2xLVDS West (960x1080 @240Hz) CLK and CTRL FE CTRL Test GPIO 3 GPIO Lines DATA 60 bit DATA 60 bit (960+32)x1080@240Hz Field, H/V-Sync, DE, CLK Vx1 ASIC TPs 3 Config. Lines Actuator Driver Test GPIO 3 ASIC TPs 3 Ref Clk OSC OSC DLP Chipset Components 3 rd Party Components CLK and CTRL (960+32)x1080@240Hz 3 VBIAS, VRST, VOFS L3 1.1V Reg L1 L2 Current Sense 1.8V VSPI L4 1.8V Reg DLPA3000 L5 DC Reg 3.3V@.2A for DLPC6421s 2.5V (to front-end chip) LDO#1 LDO#2 Fan or a programmable DC supply 1.8V@3A for DMD and DLPC6421s 1.1V@3A for DLPC6421s VIN SPI Bus (Ctrl) 4 POSENSE PWRGOOD LED_SEL 2 PROJ_ON SYSPWR (12-20V) POSENSE 1.1V 1.8V 1.8V 3.3V INTZ RESETZ PWRGOOD VLED FPGA Voltages Regulators 1.1V/1.1V_FIL 1.15V/1.15V_FIL 1.5V/1.5V_FIL 2.5V/2.5V_FIL 3.3V DDR_VTT DDR_VREF SYSPWR (12-20V) 3D L/R 1.1V 1.8V 3.3V DDR3 DATA ADDR x2 DDR3 DATA ADDR x2 Bank 1 Bank 2 JTAG Flash SPI FPGA XC7A200T- 2FBG676C4525 Output: 1080P @240Hz DLPC6421 Master DLPC6421 Slave .47 Pico 4K DMD 4-Position Actuator Front End IC Vx1: 3840x2160 @ 60Hz .47 4K UHD DMD I2C EEPROM Flash Flash 31 DLPC6421 www.ti.com DLPS117 – JULY 2018 Product Folder Links: DLPC6421 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Typical Application (continued) Figure 11. Typical 4K UHD DLPA3000 Display Application 8.2.1 Design Requirements The display controller is the digital interface between the DMD and the rest of the system. The display controller takes digital input from front end digital receivers and drives the DMD over a high speed interface. The display controller also generates the necessary signals (data, protocols, timings) required to display images on the DMD. Some systems require a dual controller to format the incoming data before sending it to the DMD. Reliable operation of the DMD is only insured when the DMD and the controller are used together in a system. In addition to the DLP devices in the chipset, other devices may be needed. Typically a Flash part is needed to store the software and firmware. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration Table 7. Crystal Port Characteristics PARAMETER NOMINAL UNIT MOSC TO GROUND Capacitance 1.5 pF MOSCZ TO GROUND Capacitance 1.5 pF Table 8. Recommended Crystal Configuration PARAMETER RECOMMENDED UNIT Crystal circuit configuration Parallel resonant Crystal type Fundamental (1st Harmonic) Crystal nominal frequency 20 MHz |
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