DLPC6421 datasheet(27/48 Pages) TI1

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DLPC6421

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DLPS117 – JULY 2018

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Feature Description (continued)

7.2.3 GPIO Interface

The DLPC6421 controller provides 83 software-programmable, general-purpose I/O pins. Each GPIO pin is

individually configurable as either input or output. In addition, each GPIO output can be either configured as

push-pull or open-drain. Some GPIO have one or more alternate-use modes, which are also software

configurable. The reset default for all GPIO is as an input signal. However, any alternate function connected to

these GPIO pins, with the exception of general purpose clocks and PWM generation, will be reset. When

configured as open-drain, the outputs must be externally pulled-up (to the 3.3-V supply). External pull-up or pull-

down resistors may be required to ensure stable operation before software is able to configure these ports.

7.2.4 Source Input Blanking

Vertical and horizontal blanking requirements for both input ports are defined as follows (See Video Timing

Parameter Definitions).

•

Minimum port 1 and port 2 vertical blanking

–

Vertical back porch (VBP): 370 µs

–

Vertical front porch (VFP): 1 line

–

Total vertical blanking (TVB): 370 µs + 2 lines

•

Minimum port1, port 2 horizontal blanking

–

Horizontal back porch (HBP): 10 pixels

–

Horizontal front porch (HFP): 0 pixels

–

Total horizontal blanking (THB): 80 pixels

7.2.5 Video Graphics Processing Delay

The DLPC6421 controller introduces a variable number of frame delays dependent on the source type and

selected processing steps performed on the source. For optimum audio/ video synchronization this delay must

be matched in the audio path. The following tables define various video delay scenarios to aid in audio matching.

Frame in table refer to source frames.

•

For 2-D sources, “N” is defined to be the ratio of the primary channel source frame rate to the display frame

rate.

•

For 3-D sources, “M” is defined to be the ratio of the primary channel source frame rate required to obtain

both the left and right image, to the display frame rate (the rate at which each eye is displayed).

Table 3. Primary Channel/Video-Graphics Processing Delay

Source

Frame Rate Conversion

FRC Type

Formatter Buffer

Total Delay

48 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

50 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

60 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

100 & 120 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

100 & 120 Hz Graphics

(3D)

1 Frame

Sync (1:2)

M Frames

1 + M Frames

240 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

DLPC6421 Datasheet(PDF) 27 Page - Texas Instruments

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