DLPC6421 datasheet(28/48 Pages) TI1

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DLPC6421

DLPS117 – JULY 2018

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Board-level pulldown resistor required.

7.2.6 Program Memory Flash

The DLPC6421 controller provides an external program memory chip select:

•

PM_CSZ_1 – dedicated CS for boot flash device (i.e. Standard NOR-type flash,

≤ 128 Mb)

The DLPC6421 controller provides enough Program Memory Address pins to support a flash device up to 128

Mb. The two most significant address bits (i.e. PM_ADDR_22 and PM_ADDR_21) are shared on pins GPIO_36

and GPIO_35 respectively. Like other GPIO pins, these pins float in a high-impedance input state following reset;

therefore, if these GPIO pins are to be reconfigured as Program Memory Address pins, they require board-level

pull-down resistors to prevent any flash address bits from floating until software is able to reconfigure the pins

from GPIO to Program Memory Address. Also note that until software reconfigures the pins from GPIO to

Program Memory Address, upper portions of flash memory are not accessible.

Table 4 shows typical GPIO_35 and GPIO36 pin configuration for various flash sizes.

Table 4. Typical GPIO_35 and GPIO_36 Pin Configurations for Various Flash Sizes

FLASH SIZE

GPIO_36 Pin Configuration

GPIO_35 Pin Configuration

32 Mb or less

PM_ADDR_22(1)

PM_ADDR_21(1)

64 Mb

128 Mb

7.2.7 Calibration and Debug Support

The DLPC6421 controller contains a test point output port, TSTPT_(7:0), which provides selected system

calibration support as well as debug support. These test points are inputs while reset is applied and switch to

outputs when reset is released. The state of these signals is sampled upon the release of system reset and the

captured value configures the test mode until the next time reset is applied. Each test point includes an internal

pull-down resistor and thus external pull-ups are used to modify the default test configuration. The default

configuration (x00) corresponds to the TSTPT_(7:0) outputs being driven low for reduce switching activity during

normal operation. For maximum flexibility, an option to jumper to an external pull-up is recommended for

TSTPT_(3:0). Note that adding pull-up to TSTPT_(7:4) may have adverse affects for normal operation and are

not recommended. Note that these external pull-ups are only sampled upon a zero to one transition on

POSENSE and thus changing their configuration after reset has been released will not have any effect until the

next time reset is asserted and released. Table 5 defines the test mode selection for 3 of the 16 programmable

scenarios defined by TSTPT_(3:0), if a test mode is not selected the system will output the default configuration

listed under Default Software Configuration.

Table 5. Test Mode Selection

No Switching

Activity

System

Calibration

ARM Debug Signal Set

Default Software Configuration

TSTPT(3:0)

Capture Value

N/A

TSTPT(0)

Vertical Sync

ARM9_Debug (0)

User Configurable (Default: VSYNC)

TSTPT(1)

Delayed CW

Index

ARM9_Debug (1)

User Configurable

TSTPT(2)

Sequence Index

ARM9_Debug (2)

User Configurable

TSTPT(3)

CW Spoke Test

ARM9_Debug (3)

User Configurable (Default: Sequence index)

TSTPT(4)

CW Revolution

Test Pt

ARM9_Debug (4)

User Configurable

TSTPT(5)

Reset Seq. Aux

Bit 0

ARM9_Debug (5)

User Configurable

TSTPT(6)

Reset Seq. Aux

Bit 1

ARM9_Debug (6)

Reserved

TSTPT(7)

Reset Seq. Aux

Bit 2

ARM9_Debug (7)

User Configurable

DLPC6421 Datasheet(PDF) 28 Page - Texas Instruments

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