AD9548 datasheet(101/111 Pages) AD

101 / 111 page

Data Sheet

AD9548

NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)

Table 142. EEPROM Control

Address

Bits

Bit Name

Description

0x0E00

[7:2]

Unused

[1]

Half rate

mode

EEPROM serial communication rate.

0 (default) = 400 kHz (normal).

1 = 200 kHz.

[0]

Write enable

EEPROM write enable/protect.

0 (default) = EEPROM write protected.

1 = EEPROM write enabled.

0x0E01

[7:5]

Unused

[4:0]

Condition

value

When set to a nonzero value (default = 0), these bits establish the condition for EEPROM downloads.

0x0E02

[7:1]

Unused

[0]

Save to

EEPROM

Upload data to the EEPROM based on the EEPROM storage sequence. This is an autoclearing bit. When

an EEPROM save/load transfer is complete, wait a minimum of 10 μs before starting the next EEPROM

save/load transfer.

0x0E03

[7:2]

Unused

[1]

Load from

EEPROM

Download data from the EEPROM. This is an autoclearing bit. When an EEPROM save/load transfer is

complete, wait a minimum of 10 μs before starting the next EEPROM save/load transfer.

[0]

Unused

EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F)

The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. The following is a

description of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage

sequence.

Table 143. EEPROM Storage Sequence for System Clock Settings

Address

Bits

Bit

Name

Description

0x0E10

[7:0]

System

clock

The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value

is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the address specified by the

next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer.

0x0E11

[7:0]

System

clock

The default value of these two registers is 0x0100. Note that Register 0x0E11 and Register 0x0E12 are the

most significant and least significant bytes of the target address, respectively. Because the previous register

contains a data instruction, these two registers define a starting address (in this case, 0x0100). The controller

stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the

10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to the system clock

parameters in the register map.

0x0E12

[7:0]

0x0E13

[7:0]

I/O

update

The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The

controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.

Table 144. EEPROM Storage Sequence for System Clock Calibration

Address

Bits

Bit Name

Description

0x0E14

[7:0]

SYSCLK

calibrate

The default value of this register is 0xA0, which the controller interprets as a calibrate instruction. The

controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.

Rev. G | Page 101 of 111

AD9548 Datasheet(PDF) 101 Page - Analog Devices

AD9548 Datasheet(HTML) 101 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL