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AD9548 Datasheet(PDF) 108 Page - Analog Devices

Part # AD9548
Description  Quad/Octal Input Network Clock Generator/Synchronizer
PDF  111 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9548 Datasheet(HTML) 108 Page - Analog Devices

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AD9548
Data Sheet
Rev. G | Page 108 of 111
CALCULATING DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients (, , , and  (see Figure 42))
relate to the time constants (T1, T2, and T3) associated with the
equivalent analog circuit for a third order loop filter (see Figure 69).
Note that AD9548 evaluation software contains a profile
designer that will compute these coefficients for you. The user
should not normally need to use these formulas.
FROM
CHARGE
PUMP
TO
VCO
R3
C3
C1
C2
Figure 69. Third Order Analog Loop Filter
The design process begins by deciding on two design
parameters related to the second order loop filter shown in
Figure 70—the desired open-loop bandwidth (fP) and phase
margin (.
FROM
CHARGE
PUMP
TO
VCO
C1
C2
Figure 70. Second Order Analog Loop Filter
An analysis of the second order loop filter leads to its primary
time constant, T1. It can be shown that T1 is expressible in terms
of fP and  as
)
cos(
)
sin(
1
P
1
T
where
P
P
f
2
.
An analysis of the third order loop filter leads to the definition
of another time constant, T3. It can be shown that T3 is
expressible in terms of the desired amount of additional
attenuation introduced by R3 and C3 at some specified
frequency offset (fOFFSET) from the PLL output frequency.
OFFSET
ATTEN
3
T
1
10 10
where
OFFSET
OFFSET
f
2
.
Note that ATTEN is the desired excess attenuation in decibels.
Furthermore, ATTEN and ωOFFSET should be chosen so that
P
f
T
5
1
3
With an expression for T1 and T3, it is possible to define an
adjusted open-loop bandwidth (fC) that is slightly less than fP. It
can be shown that ωC (fC expressed as a radian frequency) is
expressible in terms of T1, T3, and θ (phase margin) as





1
)
tan(
1
)
tan(
2
2
2
3
1
3
1
3
1
3
1
3
1
3
1
C
T
T
T
T
T
T
T
T
T
T
T
T
It can also be shown that the adjusted open-loop bandwidth
leads to T2 (the secondary time constant of the second order
loop filter) expressed as

3
1
C
2
T
T
T
2
1
Calculation of the digital loop filter coefficients requires a
scaling constant, K (related to the system clock frequency, fS),
and the PLL feedback divide ratio, D.
S
f
K
33
2
125
,
578
,
517
,
30
1
V
U
S
D
where S, U, and V are the integer and fractional feedback
divider values that reside in the profile registers. Keep in mind
that the desired integer feedback divide ratio is one more than
the stored value of S (hence, the +1 term in the equation for D
in this equation). This leads to the digital filter coefficients
given by



2
2
2
2
1
1
1
2
C
3
C
1
C
1
2
C
T
T
T
K
T
D
T


2
1
S
T
T
f
1
1
32
1
S T
f
32
3
S T
f
32
Calculation of the coefficient register values requires the
application of some special functions described as follows:
The if() function
y = if(test_statement, true_value, false_value)
where test_statement is a conditional expression (for example, x
< 3), true_value is what y equals if the conditional expression is
true, and false_value is what y equals if the conditional
expression is false.
The round() function
y = round(x)



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