AD9152 datasheet(32/103 Pages) AD

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AD9152

Data Sheet

Rev. B | Page 32 of 103

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has four identical channels. Each channel

consists of the terminators, an equalizer, a CDR circuit, and the

1:40 demux function (see Figure 38).

JESD204B data is input to the AD9152 via the SERDINx±

differential input pins per the JESD204B specification.

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200, Bit 0 = 0. In addition, each physical lane that

is not being used (SERDINx±) must be powered down. To do

so, set the corresponding Bit x for Physical Lane x in Register 0x201

to 0 if the physical lane is being used, and to 1 if it is not being used.

The AD9152 autocalibrates the input termination to 50 Ω. Before

running the termination calibration, write to Register 0x2AA

and Register 0x2AB as described in Table 34 to guarantee

proper calibration. The termination calibration begins when

The PHY termination autocalibration routine is as shown in

Table 34.

Table 34. PHY Termination Autocalibration Routine

Address

Value

Description

0x2AA1

0xB7

JESD204B interface termination configuration

0x2AB1

0x87

JESD204B interface termination configuration

0x2A7

0x01

Autotune PHY terminations

1 Register 0x2AA and Register 0x2A8 must be set to the recommend value in

Table 34 and do not appear in the register map.

The input termination voltage of the DAC is sourced externally

via the VTT pins (Pin 13 and Pin 30). Set VTT by connecting it to

SVDD12. It is recommended to ac couple the JESD204B inputs

to the JESD204B transmit device using 100 nF capacitors.

Receiver Eye Mask

The AD9152 complies with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with this mask. Figure 39 shows the receiver eye

mask normalized to the data rate interval with a VTT swing of

600 mV. See the JESD204B specification for more information

regarding the eye mask and permitted receiver eye opening.

525

–55

–525

0.5

1.00

0.35

0.65

TIME (UI)

LV-OIF-11G-SR Rx EYE MASK

Figure 39. Receiver Eye Mask

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

where:

M is the JESD204B parameter for converters per link.

L is the JESD204B parameter for lanes per link.

ByteRate = LaneRate/10

This comes from 8-bit/10-bit encoding, where each byte is

represented by 10 bits.

PClockRate = ByteRate/4

The processing clock is used for a quad-byte decoder.

FrameRate = ByteRate/F

where F is defined as octets per frame per lane.

PClockFactor = FrameRate/PClockRate = 4/F

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer-N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL VCO operates over the range of 5.75 GHz to 12.38 GHz.

In the SERDES PLL, a VCO divider block divides the VCO

clock by 2 to generate a 2.88 GHz to 6.19 GHz quadrature clock

for the deserializer cores. This clock is the input to the clock

and data recovery block that is described in the Clock and Data

Recovery section.

The reference clock to the SERDES PLL is always running at a

frequency, fREF, that is equal to 1/40 of the lane rate (PClockRate).

This clock is divided by the DivFactor value to deliver a clock to

the PFD block that is between 35 MHz and 80 MHz. Table 35

includes the respective SERDES_PLL_DIV_MODE settings for

each of the desired DivFactor options available.

Table 35. SERDES PLL Divider Settings

LaneRate (Gbps)

Divide by

(DivFactor)

SERDES_PLL_DIV_MODE

1.44 to 3.09

2.88 to 6.19

5.75 to 12.38

To enable the SERDES PLL, first set the PLL divider register

according to Table 35, and then enable the SERDES PLL by

writing 1 to Register 0x280, Bit 0.

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