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AD9152 Datasheet(PDF) 4 Page - Analog Devices |
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AD9152 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 103 page  AD9152 Data Sheet Rev. B | Page 4 of 103 DETAILED FUNCTIONAL BLOCK DIAGRAM DAC PLL POWER-ON RESET SERIAL I/O PORT CONFIG REGISTERS SYNCHRONIZATION LOGIC DAC ALIGN DETECT CLOCK DISTRIBUTION AND CONTROL LOGIC REF AND BIAS I120 DACCLK IOUT+ SYSREF RCVR DACCLK+ DACCLK– DIV (2, 4, 16, 32) CLK RECIEVER REFCLK+ REFCLK– REF RECIEVER DIGITAL GAIN [10:0] PFIR INV SINC COARSE DDS DOWNSTREAM PROTECTION MODULUS DDS PHASE ADJUST DC OFFSET I/Q ±( f DAC/4), ±(fDAC/8) × N NCO FINE MODULATION PDP JESD204B ERRORS SPI TXEN I DAC 16-BIT Q DAC 16-BIT PLL_CTRL PLL_LOCK DACCLK SYSREF+ SYSREF– SYNCOUT+ SYNCOUT– PLL (40×) DIV DACCLK AD9152 HB2 HB1 MODE CONTROL HB2 HB3 HB3 HB1 SERDIN3± SERDIN0± IOUT– QOUT+ QOUT– Figure 2. Detailed Functional Block Diagram |
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