AD9152 datasheet(73/103 Pages) AD

73 / 103 page

Data Sheet

AD9152

Rev. B | Page 73 of 103

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

SYNCOUT±, SYSREF±, and DACCLK±/REFCLK± Signals

The SYNCOUT± and SYSREF± signals on the AD9152 are low

speed LVDS differential signals. Use controlled impedance

traces routed with 100 Ω differential impedance and 50 Ω to

ground when routing these signals. As with the SERDIN0± to

SERDIN3± data pairs, it is important to keep these signals

separated from potential noise sources such as high speed

digital signals and noisy supplies.

Separate the SYNCOUT± signal from other noisy signals,

because noise on the SYNCOUT± might be interpreted as a

request for K characters.

It is important to keep similar trace lengths for the

DACCLK±/REFCLK± and SYSREF± signals from the clock

source to each of the devices on either end of the JESD204B

links, see Figure 77. If using a clock chip that can tightly control

the phase of DACCLK±/REFCLK± and SYSREF±, the trace

length matching requirements are greatly reduced.

CLOCK SOURCE

(AD9516-1, AD9525,

AND AD9528)

LANE 0

LANE 1

LANE N – 1

LANE N

DEVICE CLOCK

SYSREF

SYSREF TRACE LENGTH

DEVICE CLOCK TRACE LENGTH

DEVICE

Figure 77. SYSREF± Signal and Device Clock Trace Length

AD9152 Datasheet(PDF) 73 Page - Analog Devices