AD9152 datasheet(39/103 Pages) AD

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Data Sheet

AD9152

Rev. B | Page 39 of 103

Sync Procedure

The procedure for enabling the sync is as follows:

Set the desired sync processing mode. The sync processing

mode settings are listed in Table 39.

For Subclass 1, set the error window according to the

uncertainty of the SYSREF± signal relative to the DAC

clock and the tolerance of the application for deterministic

latency uncertainty. The sync window tolerance settings

are given in Table 40.

Enable sync by writing 1 to SYNCENABLE (Register 0x03A,

Bit 7).

If in one shot mode, arm the sync machine by writing 1 to

SYNCARM (Register 0x03A, Bit 6).

If in Subclass 1, ensure that at least one SYSREF± pulse is

sent to the device.

Check the status by reading the following bit fields:

a) SYNCBUSY (Register 0x03B, Bit 7) = 0 to indicate that

the sync logic is no longer busy.

b) SYNCLOCK (Register 0x03B, Bit 3) = 1 to indicate that

the signals are aligned. This bit updates on every phase

check.

c) SYNCWLIM (Register 0x03B, Bit 1) = 0 to indicate

that the phase error is not beyond the specified error

window. This bit updates on every phase check.

d)SYNCROTATE (Register 0x03B, Bit 2) = 1 if the phases

were not aligned before the sync and a clock

alignment occurred. This bit is sticky and can be

cleared only by writing to SYNCCLRSTKY control

bit (Register 0x03A, Bit 5).

e) SYNCTRIP (Register 0x03B, Bit 0) = 1 to indicate that

the alignment edge was received and the phase

check occurred. This bit is sticky and can be cleared

only by writing to SYNCCLRSTKY control bit

(Register 0x03A, Bit 5).

Table 39. Sync Processing Modes

Sync Processing Mode

SYNCMODE (Register 0x03A, Bits[3:0])

One Shot

0x01

Continuous

0x02

One Shot Then Monitor

0x09

Table 40. Sync Window Tolerance

Sync Error Window Tolerance

(DAC Clock Cycles)

ERRWINDOW

(Register 0x034, Bits[2:0])

±½

0x00

±1

0x01

±2

0x02

±3

0x03

±4

0x04

±5

0x05

±6

0x06

±7

0x07

LMFC Sync IRQ

The sync status bits (SYNCLOCK, SYNCROTATE, SYNCTRIP,

and SYNCWLIM) are available as IRQ events.

Use Register 0x021, Bits[3:0] to enable the sync status bits, and

then use Register 0x025, Bits[3:0] to read back their statuses and

to reset the IRQ signals.

See the Interrupt Request Operation section for more information.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout each system. Data traversing from one clock

domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to

nonrepeatable latencies across the link from power cycle to

power cycle with each new link establishment. Section 6 of the

JESD204B specification addresses the issue of deterministic

latency with mechanisms defined as Subclass 1 and Subclass 2.

The AD9152 supports JESD204B Subclass 0 and Subclass 1 opera-

tion, but not Subclass 2. Write the subclass to Register 0x301,

Bits[2:0] and once per link to Register 0x458, Bits[7:5].

Subclass 0

Subclass 0 mode does not require any signal on the SYSREF±

pins, which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same

LMFC cycle.

Minor Subclass 0 Caveats

Because the AD9152 requires an ILAS, the nonmultiple

converter single lane (NMCDA-SL) case from the JESD204A

specification is supported only when using the optional ILAS.

Error reporting using SYNCOUT± is not supported when using

Subclass 0 with F = 1.

Subclass 1

Subclass 1 mode gives deterministic latency and allows links to be

synced to within ½ a DAC clock period. It requires an external

SYSREF± signal that is accurately phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.

•

SYSREF± signal distribution skew within the system must

be less than the desired uncertainty.

•

SYSREF± setup and hold time requirements must be met

for each device in the system.

•

The total latency variation across all lanes, and devices

must be ≤10 PClock periods. This includes both variable

delays and the variation in fixed delays from lane to lane

and device to device in the system.

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