AD9152 datasheet(29/103 Pages) AD

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Data Sheet

AD9152

Rev. B | Page 29 of 103

Link Delay Setup

Use LMFCVar and LMFCDel to impose delays such that all

lanes in a system arrive in the same LMFC cycle.

The unit used internally for delays is the period of the internal

processing clock (PClock), whose rate is 1/40th of the lane rate.

Delays that are not in PClock cycles must be converted before

they are used.

Some useful internal relationships are defined below:

PClock period = 40/LaneRate

The PClock period can be used to convert from time to PClock

cycles when needed.

PClockFactor = 4/F (Frames per PClock)

PClockFactor is used to convert from units of PClock cycles to

frame clock cycles, which is needed to set LMFCDel in Subclass 1.

PClocksPerMF= K/PClockFactor (PClocks per LMFC cycle)

where PClocksPerMF is the number or PClock cycles in a

multiframe cycle.

The values for PClockFactor and PClockPerMF are given per

JESD204B mode in Table 30.

Table 30. PClockFactor and PClockPerMF Per JESD204B Mode

JESD204B Mode ID

PClockFactor

PClockPerMF (K = 32)

PClockPerMF (K = 16)

N/A1

1 N/A means not applicable.

With Known Delays

With information about all the system delays, LMFCVar and

LMFCDel can be calculated directly.

RxFixed (the fixed receiver delay in PClock cycles) and RxVar

(the variable receiver delay in PClock cycles) can be found in

Table 8. TxFixed (the fixed transmitter delay in PClock cycles)

and TxVar (the variable receiver delay in PClock cycles) can be

found in the data sheet of the transmitter used. PCBFixed (the

fixed PCB trace delay in PClock cycles) can be extracted from

the software; because this is generally much smaller than a

PClock cycle, it can also be omitted. For both the PCB and

transmitter delays, convert the delays into PClock cycles.

For each lane,

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

Across lanes, links, and devices:

MinDelay is the minimum of all MinDelayLane values.

MaxDelay is the maximum of all MaxDelayLane values.

For safety, add a guard band of 1 PClock cycle to each end of

the link delay as in the following equations:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

Note that if LMFCVar must be more than 10, the AD9152

cannot tolerate the variable delay in the system.

For Subclass 1,

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

For Subclass 0,

LMFCDel = (MinDelay − 1) % PClockPerMF

Program the same LMFCDel and LMFCVar across all links and

devices.

See the Link Delay Setup Example, with Known Delays section

for an example calculation.

Without Known Delays

If comprehensive delay information is not available or known,

the AD9152 can read back the link latency between the LMFCRX

and the last arriving LMFC boundary in PClock cycles. This

information is then used to calculate LMFCVar and LMFCDel.

For each link (on each device),

Power up the board.

Follow the steps in Table 15 through Table 23 of the Device

Setup Guide.

Set the subclass and perform a sync. For one shot sync,

perform the writes in Table 31. See the Syncing LMFC

Signals section for alternate sync modes.

Record DYN_LINK_LATENCY_0 (Register 0x302) as a

value of Delay for that link and power cycle.

Repeat Steps 1 to Step 4 twenty times for each device in the system.

Keep a single list of the Delay values across all runs and devices.

Table 31. Register Configuration and Procedure for One

Shot Sync

Addr.

Bit.

No.

Value1

Variable

Description

0x301

Subclass

Set the subclass

0x03A

0x01

Set sync mode to one

shot sync

0x03A

0x81

Enable the sync

machine

0x03A

0xC1

Arm the sync machine

SYSREF±

If Subclass = 1, ensure

that at least one

SYSREF± edge is sent

to the device

0x300

Enable the link

ChkSmMd

See the JESD204B

Setup section

Enable the link

1 0x denotes a register value that the user must fill in. See the Variable and

Description columns for information on selecting the appropriate register value.

The list of delay values is used to calculate LMFCDel and

LMFCVar, but first some of the delay values may need to be

remapped.

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