AD9152 datasheet(7/103 Pages) AD

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Data Sheet

AD9152

Rev. B | Page 7 of 103

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SPI

Maximum Clock Rate

SCLK

IOVDD = 1.8 V

MHz

Minimum SCLK Pulse Width

High

tPWH

Low

tPWL

SDIO to SCLK

Setup Time

tDS

Hold Time

tDH

SDO to SCLK

Data Valid Window

tDV

CS to SCLK

Setup Time

tSCS

Hold Time

tHCS

1 See Table 3 and Table 4 for detailed specifications for the DAC update rate conditions.

2 The maximum speed for 1× interpolation is limited by the JESD2040B interface. See Table 4 for details.

3 See Table 4 for detailed specifications for JESD2040B speed conditions.

4 K and S are JESD204B transport layer parameters. See Table 41 for the full definitions.

5 See Table 5 for detailed specifications for SYSREF± to DAC clock timing conditions.

MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V,

SVDD12 = 1.2 V, SDVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

MAXIMUM DAC UPDATE RATE

DVDD12, CVDD12 = 1.2 V ± 5%

1.85

GSPS

DVDD12, CVDD12 = 1.3 V ± 2%

2.25

GSPS

JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V,

SVDD12 = 1.2 V, SDVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

HALF RATE

SVDD12, SDVDD12, PLLVDD12 = 1.2 V ± 5%

5.75

11.00

Gbps

SVDD12, SDVDD12, PLLVDD12 = 1.3 V ± 2%

5.75

12.38

Gbps

FULL RATE

SVDD12, SDVDD12, PLLVDD12 = 1.2 V ± 5%

2.88

5.53

Gbps

SVDD12, SDVDD12, PLLVDD12 = 1.3 V ± 2%

2.88

6.19

Gbps

OVERSAMPLING

SVDD12, SDVDD12, PLLVDD12 = 1.2 V ± 5%

1.44

2.69

Gbps

SVDD12, SDVDD12, PLLVDD12 = 1.3 V ± 2%

1.44

3.09

Gbps

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