AD9152 datasheet(65/103 Pages) AD

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Data Sheet

AD9152

Rev. B | Page 65 of 103

the VCO. A low noise VCO is tunable over an octave with an

oscillation range of 6 GHz to 12 GHz.

The clock multiplication circuit operates such that the VCO

outputs a frequency, fVCO.

fVCO = fDAC × LODivFactor

(3)

From Equation 2, the DAC sample clock frequency, fDAC, equals

RefDivFact

BCount

REF

DAC

= 2

(4)

The LODivFactor is chosen to keep fVCO in the operating range

between 6 GHz and 12 GHz. The valid values for LODivFactor

are 4, 8, and 16. Each LODivFactor maps to a LO_DIV_MODE

value. The LO_DIV_MODE (Register 0x08B, Bits[1:0]) is

programmed as described in Table 71.

Table 71. DAC VCO Divider Selection

DAC Frequency

Range (MHz)

Divide by Factor

(LODivFactor)

LO_DIV_MODE,

>1500

750 to 1500

420 to 750

Table 72 lists some common frequency examples for the

RefDivFactor, LODivFactor, and BCount values that are needed

to configure the PLL properly.

Table 72. Common Frequency Examples

Freq.

(MHz)

fDAC (MHz)

fVCO

(MHz)

RefDiv-

Factor

LODiv-

Factor

BCount

368.64

1474.56

11796.48

184.32

1474.56

11796.48

307.2

1228.88

9831.04

122.88

983.04

7864.35

61.44

983.04

7864.35

491.52

1966.08

7864.35

245.76

1966.08

7864.35

Temperature Tracking

When properly configured, the device automatically selects one of

the 512 VCO bands. The PLL settings selected by the device ensure

that the PLL remains locked over the full −40°C to +85°C operating

temperature range of the device without further adjustment. The

PLL remains locked over the full temperature range even if the

temperature during initialization is at one of the temperature

extremes.

To properly configure temperature tracking, See Figure 17 and

Figure 18 and the fVCO dependent SPI writes shown in Table 73.

Table 73. DAC PLL VCO Control Lookup Table

VCO

Frequency

Range (GHz)

0x1B6

Setting

0x1BB

Setting

0x1B5

Setting

0x1C5

Setting

fVCO < 6.84

0x49

0x1A

0xC7

0x08

6.84 ≤ fVCO <

8.69

0x49

0x12

0xC9

0x06

8.69 ≤ fVCO <

10.54

0x4D

0x04

0xC9

0x06

fVCO ≥ 10.54

0x4D

0x04

0xC9

0x06

STARTING THE PLL

The programming sequence for the DAC PLL is as follows:

Use the equations in the Clock Multiplication

Relationships section to find fVCO, fREF, BCount,

RefDivMode, and LODivMode.

Program the registers in Figure 17 and Figure 18

Program the value of LODivMode into Register 0x08B,

Bits[1:0].

Program the value of BCount into Register 0x085,

Bits[7:0].

Program the value of RefDivMode into Register 0x08C,

Bits[2:0].

Based on the fVCO found in Step 1, write the temperature

tracking registers as shown in Table 73.

Enable the DAC PLL synthesizer by setting Register 0x083,

Bit 4 to 1.

is completed and is valid.

that the DAC PLL has reached the upper or lower edge of its

operating band, respectively. If either of these bits are high,

recalibrate the DAC PLL by setting Register 0x083, Bit 7 to 0

and then 1.

DAC PLL IRQ

The DAC PLL lock and lost signals are available as IRQ events.

Use Register 0x01F, Bits[7:6] to enable these signals, and then

use Register 0x023, Bits[7:6] to read back their statuses and

reset the IRQ signals. See the Interrupt Request Operation

section for more information.

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