AD9152 datasheet(30/103 Pages) AD

30 / 103 page

AD9152

Data Sheet

Rev. B | Page 30 of 103

The maximum possible value for DYN_LINK_LATENCY is one

less than the number of PClocks in a multiframe (PClocksPerMF).

It is possible that a rollover condition may be encountered,

meaning the set of recorded Delay values might roll over the

edge of a multiframe. If so, Delay values may be near both 0 and

PClocksPerMF. If this occurs, add PClocksPerMF to the set of

values near 0.

For example, for Delay value readbacks of 6, 7, 0, and 1, the 0

and 1 Delay values must be remapped to 8 and 9, making the

new set of Delay values 6, 7, 8, and 9.

Across power cycles, links, and devices.

•

MinDelay is the minimum of all Delay measurements.

•

MaxDelay is the maximum of all Delay measurements.

For safety, a guard band of 1 PClock cycle is added to each end

of the link delay and calculate LMFCVar and LMFCDel with

the following equation:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

Note that if LMFCVar must be more than 10, the AD9152

cannot tolerate the variable delay in the system.

For Subclass 1,

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

For Subclass 0,

LMFCDel = (MinDelay − 1) % PClockPerMF

Program the same LMFCDel and LMFCVar across all links and

devices.

See the Link Delay Setup Example, Without Known Delays

section for an example calculation.

CROSSBAR SETUP

physical lanes (SERDINx±) to logical lanes used by the SERDES

deframers.

Table 32. Crossbar Registers

Address

Bits

Logical Lane

0x308

[2:0]

LOGICAL_LANE0_SRC

0x308

[5:3]

LOGICAL_LANE1_SRC

0x309

[2:0]

LOGICAL_LANE2_SRC

0x309

[5:3]

LOGICAL_LANE3_SRC

Write each LOGICAL_LANEx_SRC with the number (x) of the

desired physical lane (SERDINx±) from which to receive data.

By default, all logical lanes use the corresponding physical lane

as their data source. For example, by default LOGICAL_LANE0_

SRC = 0, meaning Logical Lane 0 receives data from Physical

Lane 0 (SERDIN0±). If instead the user wants to use SERDIN3±

as the source for Logical Lane 0, the user must write

LOGICAL_LANE0_SRC = 3.

AD9152 Datasheet(PDF) 30 Page - Analog Devices

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