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Datasheet

eCompass BMC150

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BST-BMC150-DS000-04 | Revision 1.0 | July 2014

Bosch Sensortec

third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.

Note: Specifications within this document are subject to change without notice. Not intended for publication.

fifo_config_1, (0x30) fifo_config_0 and (0x3F) fifo_data register. It is possible to enter normal

mode by performing a softreset as described in chapter.7.6.

Suspend mode is entered (left) by writing ´1´ (´0´) to the (0x11) suspend bit after bit (0x12)

lowpower_mode has been set to ‘0’. Although write access to registers is supported at the full

interface clock speed (SCL or SCK), a waiting period must be inserted between two consecutive

write cycles (please refer also to section 8.2.1).

In standby mode the analog part is powered down, while the digital part remains largely

operational. No data acquisition is performed. Reading and writing registers is supported

without any restrictions. The latest acceleration data and the content of all configuration

registers are kept. Standby mode is entered (left) by writing ´1´ (´0´) to the (0x11) suspend bit

after bit (0x12) lowpower_mode has been set to ‘1’. It is also possible to enter normal mode by

performing a softreset as described in chapter 7.6.

In low-power mode 1, the device is periodically switching between a sleep phase and a wake-

up phase. The wake-up phase essentially corresponds to operation in normal mode with

complete power-up of the circuitry. The sleep phase essentially corresponds to operation in

suspend mode. Low-power mode is entered (left) by writing ´1´ (´0´) to the (0x11) lowpower_en

bit after bit (0x12) lowpower_mode has been set to ‘0’. Read access to registers is possible

except from the (0x3F) fifo_data register. However, unless the register access is synchronised

with the wake-up phase, the restrictions of the suspend mode apply.

Low-power mode 2 is very similar to low-power mode 1, but register access is possible at any

time without restrictions. It consumes more power than low-power mode 1. In low-power mode 2

the device is periodically switching between a sleep phase and a wake-up phase. The wake-up

phase essentially corresponds to operation in normal mode with complete power-up of the

circuitry. The sleep phase essentially corresponds to operation in standby mode. Low-power

mode is entered (left) by writing ´1´ (´0´) to the (0x11) lowpower_en bit with bit (0x12)

lowpower_mode set to ‘1’.

The timing behaviour of the low-power modes 1 and 2 depends on the setting of the (0x12)

sleeptimer_mode bit. When (0x12) sleeptimer_mode is set to ‘0’, the event-driven time-base

mode (EDT) is selected. In EDT the duration of the wake-up phase depends on the number of

samples required by the enabled interrupt engines. If an interrupt is detected, the device stays

in the wake-up phase as long as the interrupt condition endures (non-latched interrupt), or until

the latch time expires (temporary interrupt), or until the interrupt is reset (latched interrupt). If no

interrupt is detected, the device enters the sleep phase immediately after the required number

of acceleration samples have been taken and an active interface access cycle has ended. The

EDT mode is recommended for power-critical applications which do not use the FIFO. Also,

EDT mode is compatible with legacy BST sensors.

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