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SYNPWM Datasheet(PDF) 31 Page - Feeling Technology Corp.

Part # SYNPWM
Description  EPROM-Based 8-Bit Microcontroller with 10 bit ADC
PDF  57 Pages
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Manufacturer  FEELING [Feeling Technology Corp.]
Direct Link  http://www.feeling-tech.com.tw/
Logo FEELING - Feeling Technology Corp.

SYNPWM Datasheet(HTML) 31 Page - Feeling Technology Corp.

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FM8P73B
Web site: http://www.feeling-tech.com.tw
Rev1.0 Nov 20, 2013
P.31/FM8P73B
FEELING
TECHNOLOGY
2.7
Interrupt
The FM8P73B has three kinds of interrupt sources:
1.
8 External IOB<0:7> pin changed interrupt
2.
3 Timers underflow interrupt (or PWM interrupt)
3.
ADC conversion completion interrupt
INTFLAG is the interrupt flag register that recodes the interrupt requests to the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/ disabled through their corresponding enable bits in INTEN
register regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit
will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address
3FEh. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
2.7.1
PORTB<0:7> External Interrupt and Wakeup Function
The external interrupt on PORTB<0:7> are selected by INTPB<0:7> and PBIE (INTEN<5>). When the device is
in normal mode and the specified IO status changed, the interrupt event will be triggered and the program will
jump to 3FEh.
When the device is in sleep mode, those interrupts can also be used as an external wakeup signal. The device
will restart system clock and the program will jump to 3FEh after startup timer timeout.
Example 2.6: External IOB0 pin change interrupt
Address
Code
NA
#include
<8P73B.ASH>
…
n
MOVIA
0xFF
n+1
MOVAR
IOSTB
;Set Port B as input
n+2
MOVIA
0xA0
n+3
MOVAR
INTEN
;Enable global & Port B interrupt
n+4
MOVIA
0xDF
n+5
MOVAR
INTFALG
;Clear PBIF flag(Note1)
n+6
MOVR
PORTB,R
;Update Port B pin status
n+7
MOVIA
0x01
n+8
MOVAR
INTPB
;Set IOB0 pin change
…
…
…
N/A
ISR:
;In this example, ISR define at 0x200
200
…
;User Port B pin change ISR code
200+n
MOVIA
0xDF
200+n+1
MOVAR
INTFLAG
;Clear PBIF flag(Note1)
200+n+2
RETFIE
3FE
GOTO
ISR
3FF
GOTO
START
Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).
2. Interrupt save status code is not shown in this example.
1. IOB0 pin change
2. Return from ISR



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