GS3281 datasheet(64/97 Pages) SEMTECH

64 / 97 page

GS3281

Final Data Sheet

Rev.7

PDS-061453

January 2019

64 of 97

Semtech

Proprietary & Confidential

www.semtech.com

REF_CLK_

MODE

RSVD

15:2

R/W

Reserved - do not modify.

CFG_REF_CLK_MODE_



MANUAL

1R/W

Manual external reference mode



selection:



0 = External reference clock mode



1 = Referenceless mode

Controls reference clock mode when



CFG_REF_CLK_MODE_AUTO = 0.

CFG_REF_CLK_MODE_



AUTO

0R/W

Automatic external reference selection



mode.



0 = Disable auto mode



1 = Enable auto mode

In auto mode, the device automatically



switches to reference clock mode when



the reference clock is detected. When



auto mode is disabled, reference clock



mode is controlled by



CFG_REF_CLK_MODE_MANUAL.

Note: Once the device has been

switched to external reference mode,

either manual or automatically, it can

not be manually set back to

referenceless mode unless it is followed

by a device reset.

FACTORY_

CDR_

PARAMETERS

RSVD

15:4

R/W

Reserved - do not modify.

PHASE_MODE

3:2

R/W

Set to 3h when using a PRBS7 signal or

similar repetitive short pattern.

CFG_MIN_LBW

R/W

To maximize loop bandwidth of PLL and

consequently IJT of CDR, set this

parameter to 0.

RSVD

R/W

Reserved - do not modify.

RSVD

15:0

R/W

808

Reserved - do not modify.

Table 5-3: Control Register Descriptions (Continued)

Addressh

Name

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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