PC8374T datasheet(17/48 Pages) NSC

17 / 48 page

1.0 Signal/Pin Connection and Description (Continued)

Revision 1.1

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1.4.13 Configuration Straps and Testing

1.4.14 Power and Ground

Signal

Pin(s)

I/O Buffer Type Power Well

Description

BADDR

INTS

VDD3

Base Address. Sampled at VDD Power-Up reset to determine

the base address of the configuration Index-Data register pair,

as follows:

– No pull-down resistor (default)

- 2Eh-2Fh

– 10 K

Ω1 external pull-down resistor - 4Eh-4Fh

The external pull-down resistor must be connected to VSS.

1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended

for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 K

Ω. If, however, a TTL

transceiver device is used, the value of the external pull-down resistor must be 470

Ω, and since the Serial Port

pins are not able to drive this load, the external pull-down resistor must be disconnected tEPLV after VDD3

power-up (see “VDD Power-Up Reset” on page 30).

VsbStrap1

117

INTS

VSB3

Vsb Strap 1. Reserved strap input function for National use.

VddStrap1

122

INTS

VDD3

Vdd Strap 1. Reserved strap input function for National use.

VddStrap2

125

INTS

VDD3

Vdd Strap 2. General-Purpose strap input function.

TRIS

INTS

VDD3

TRI-STATE Device. Sampled at VDD Power-Up reset to force

the device to float all its output and I/O pins, as follows:

– No pull-down resistor (default)

- normal pin operation

– 10 K

Ω1 external pull-down resistor - floating device pins

The external pull-down resistor must be connected to VSS.

When TRIS is set to 0 (by an external pull-down resistor), TEST

must be 1 (left unconnected).

TEST

INTS

VDD3

XOR Tree Test Mode. Sampled at VDD Power-Up reset to force

the device pins into a XOR tree configuration, as follows:

– No pull-down resistor (default)

- normal device operation

– 10 K

Ω1 external pull-down resistor - pins configured as XOR

tree.

When TEST is set to 0 (by an external pull-down resistor), TRIS

must be 1 (left unconnected).

XOR_OUT

O4/8

VDD3

XOR Tree Output. All the device pins (except power type and

analog type pins) are internally connected in a XOR tree structure.

Signal

Pin(s)

I/O Buffer Type

Power

Well

Description

VSS

8, 29, 46, 58,

78, 96, 110

IGND

Ground. Ground connection for both core logic and I/O buffers,

for the Main, Standby and Battery power supplies.

VDD3

6, 31, 49, 60

PWR

Main 3.3V Power Supply. Powers the I/O buffers of the legacy

peripherals and the LPC interface.

VSB3

76, 93, 107

PWR

Standby 3.3V Power Supply. Powers the I/O buffers of the

GPIO ports, SWC, Glue Functions, TPM Health Management

and the on-chip Core power converter.

VCORF

I/O

PWR

On-Chip Core Power Converter Filter. On-chip Core power

converter output. An external 1

µF ceramic filter capacitor must

be connected between this pin and VSS.

VCORF2

102

I/O

PWR

On-Chip Core Power Converter Filter. On-chip Core power

converter output. An external 1

µF ceramic filter capacitor must

be connected between this pin and VSS.

PC8374T Datasheet(PDF) 17 Page - National Semiconductor (TI)

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