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PC8374T Datasheet(PDF) 20 Page - National Semiconductor (TI) |
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PC8374T Datasheet(HTML) 20 Page - National Semiconductor (TI) |
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20 / 48 page ![]() 1.0 Signal/Pin Connection and Description (Continued) www.national.com 20 Revision 1.1 GPO11 117 VSB3 PU30 Programmable1 GPO12-13 122, 125 VDD3 PU30 Programmable1 Glue Functions PWRGD_PS 82 VSB3 PU90 CPU_PRESENT 83 VSB3 PU90 PRIMARY_HD 67 VDD3 PU90 SECONDARY_HD 68 VDD3 PU90 SCSI 69 VDD3 PU90 Trusted Platform Module (TPM) TPM_PP 123 VSB3 PD30 Programmable7 IOPA6 123 VSB3 PU30/PD30 Programmable8 IOPA0, IOPA1 101, 91 VSB3 PU30 Programmable8 Strap Configuration BADDR 30 VDD3 PU30 Strap9 TRIS 26 VDD3 PU30 Strap9 TEST 27 VDD3 PU30 Strap9 VsbStrap1 117 VSB3 PU30 Strap10 VddStrap1 122 VDD3 PU30 Strap9 VddStrap2 125 VDD3 PU30 Strap9 1. Default at reset: enabled. 2. Enabled only when the OD6 buffer type is selected (OD6 is the default at reset). 3. Alternate function at reset: enabled. 4. Default at reset: PD enabled. 5. Default at reset: disabled. 6. Alternate function at reset: disabled. 7. Controlled by TPM. Default at reset: enabled. 8. Controlled by TPM. Default at reset: disabled. 9. Active only during VDD Power-Up reset. 10. Active only during VSB Power-Up reset. Table 3. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin(s) Power Well Type Comments |
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