PC8374T datasheet(2/48 Pages) NSC

2 / 48 page

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Revision 1.1

Features

Trusted Platform Module (TPM)

■ TCG 1.1b compliant

■ Processing Unit

— 16-bit embedded RISC processor core

■ Internal Memory

— On-chip Non-Volatile memory for secure storage

— On-chip data RAM

■ Host Interface

— Using LPC Bus

— Command/Data/Status standard interface

■ Secured General-Purpose I/O (GPIO)

— Internal processor controlled

— Three GPIO pins, one used for Physical Presence

— I/O pins individually configured as input or output

— Configurable internal pull-up resistors

— Owner authorization control

■ Power Management Controller (PMC); power modes,

switched by software or hardware

■ TPM Firmware

— VSB3 RAM-based storage for loadable keys

■ Tamper Resistance

— Clock Jitter protection

❏

Protection on reference clock

❏

Protection of security functions from LPC clock

jitter

— Power analysis resistance

— Low and High Frequency monitor

— Voltage attack detector

❏

Low Voltage

❏

Glitch and brownout detector

— Secure storage contents protection

— Permanent disable of all TPM test mechanisms

when locked

System Health Support

■ SensorPath interface to sensors optimizes digital/analog

partitioning

— Simplifies board design and routing

— Supports distributed sensors and centralized control

— Health monitoring is self-contained and requires

minimal host attention

— Faster boot time

— Off loads SMBus, and enables ASF compliance

■ Fan Monitor and Control

— Three PWM-based fan controls

— Four 16-bit resolution tachometer inputs

— Software or local temperature feedback control

■ Heceta6-compatible register set accessible via the LPC

interface and SMBus

— Supports the following combinations of LMxx devices:

❏

LM96011

❏

LM96011 and LM95010

❏

LM96012

❏

LM96010

— Simultaneous read support via LPC interface and SMBus

General-Purpose Modules

■ All 16 GPIO pins powered by VSB3

■ Each pin individually configured as input or output

■ Programmable features for each output pin:

— Drive type (open-drain, push-pull or TRI-STATE)

— TRI-STATE

detection

falling

VDD3 for

VSB3-powered pins driving VDD-supplied devices

■ Programmable option for internal pull-up resistor on

each input pin (some with internal pull-down resistor op-

tion)

■ Lock option for the configuration and data of each output

■ 15 GPIO pins generate IRQ/SIOPME/SMI for wake-up

events; each GPIO has separate:

— Enable control of event status routing to IRQ

— Enable control of event status routing to SIOPME

— Polarity and edge/level selection

❏

Programmable debouncing

Glue Functions

■ Generates the power-related signals:

— Main Power good

— Power distribution control (for switching between

Main and Standby regulators)

— Resume reset (Master Reset) according to the 5V

standby supply status

— Main power supply turn on (PS_ON)

■ Voltage translation between 2.5V or 3.3V levels (DDC) and

5V levels (VGA) for the SMBus serial clock and data signals

■ Isolation circuitry for the SMBus serial clock and data signals

■ Buffers PCI_RESET to generate three reset output signals

■ Generates “highest active supply” reference voltage

— Based on 3.3V and 5V Main supplies

— Based on 3.3V and 5V Standby supplies

■ High-current LED driver control for Hard Disk Drive

activity indication

■ Software selectable alternative functionality, through pin

multiplexing

PC8374T Datasheet(PDF) 2 Page - National Semiconductor (TI)

PC8374T Datasheet(HTML) 2 Page - National Semiconductor (TI)

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