PC8374T datasheet(16/48 Pages) NSC

16 / 48 page

1.0 Signal/Pin Connection and Description (Continued)

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Revision 1.1

PRIMARY_HD

INTS4

VDD3

Primary Drive. Active (low) level indicates that the primary

IDE drive is active.

SECONDARY_HD 68

INTS4

VDD3

Secondary Drive. Active (low) level indicates that the

secondary IDE drive is active.

SCSI

INTS4

VDD3

SCSI Drive. Active (low) level indicates that the SCSI drive

is active.

HD_LED

OD12

VDD3

Hard Drive LED. Red LED driver. When low, indicates that

at least one drive is active.

CC_DDCSCL

113

I/O

SWSM

VSB3

Chipset Cluster (2.5V or 3.3V) Level DDC Serial Clock.

SMBus serial clock signal with 2.5V or 3.3V logic levels for

Data Display Channel (DDC) interface. External pull-up

resistor to VDD3 or 2.5V is required.

5V_DDCSCL

114

I/O

SWSM

VSB3

5V Level DDC Serial Clock. SMBus serial clock signal with

5V logic levels for VGA monitor interface. External pull-up

resistor to VDD5 is required.

CC_DDCSDA

115

I/O

SWSM

VSB3

Chipset Cluster (2.5V or 3.3V) Level DDC Serial Data.

SMBus serial data signal with 2.5V or 3.3V logic levels for

DDC interface. External pull-up resistor to VDD3 or 2.5V is

required.

5V_DDCSDA

116

I/O

SWSM

VSB3

5V Level DDC Serial Data. SMBus serial data signal with

5V logic levels for VGA monitor interface. External pull-up

resistor to VDD5 is required.

SMB1_SCL

I/O

SWSM

VSB3

Bus 1 Serial Clock. Serial clock signal of SMBus 1 (3.3V logic

levels). External pull-up resistor to the 3.3V supply is required.

SMB2_SCL

I/O

SWSM

VSB3

Bus 2 Serial Clock. Serial clock signal of SMBus 2 (3.3V logic

levels). External pull-up resistor to the 3.3V supply is required.

SMB1_SDA

I/O

SWSM

VSB3

Bus 1 Serial Data. Serial data signal of SMBus 1 (3.3V logic

levels). External pull-up resistor to the 3.3V supply is required.

SMB2_SDA

I/O

SWSM

VSB3

Bus 2 Serial Data. Serial data signal of SMBus 2 (3.3V logic

levels). External pull-up resistor to the 3.3V supply is required.

PCIRST_OUT

O14/14

VSB3

PCI Reset Output. PCI system reset. PCIRST_OUT is a

buffered copy of PCI_RESET when VDD3 is on, and it is held

at low level when VDD3 is off.

PCIRST_OUT2

O14/14

VSB3

PCI Reset Output 2. PCI system reset (same behavior as

PCIRST_OUT above).

IDE_RSTDRV

OD6

VDD3

IDE Reset Output. IDE drive reset. IDE_RSTDRV is a

buffered copy of PCI_RESET when VDD3 is on, and it is

floating when VDD3 is off.

Signal

Pin(s) I/O Buffer Type Power Well

Description

PC8374T Datasheet(PDF) 16 Page - National Semiconductor (TI)

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