PC8374T datasheet(32/48 Pages) NSC

32 / 48 page

2.0 Device Characteristics (Continued)

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Revision 1.1

Low-Frequency Clock Timing

Figure 10. Internal 32 KHz (INT32K) and CLOCKO32 Timing

Symbol Figure Internal Clock Parameters Reference Conditions

INT32K

Units

Min

Typ

Max

tCP

Clock Period1

(50%-50%)

1. Not tested. Guaranteed by characterization.

After VSB3 power-up

21.3623

30.517578

39.6728

µs

tCPL

Clock Period1

(50%-50%)

After CLOCKI14 valid

30.2124

30.517578

30.8227

When VDD3 does not

exist

27.465820

30.517578

33.569336

FCK

−

Clock Frequency

After VSB3 power-up

F32TYP − 30%

32.768

(F32TYP)

F32TYP + 30%

KHz

FCKL

Clock Frequency

After CLOCKI14 valid

F32TYP − 1%

32.768

(F32TYP)

F32TYP + 1%

When VDD3 does not

exist

F32TYP − 10%

32.768

(F32TYP)

F32TYP + 10%

t32KW

Clock wake-up time1

VSB3 stable to clock

start toggling

5ms

t32KVAL

Clock valid time1

Clock start toggling to

clock valid

1ms

32.768 KHz

t32KW

VSB3 (Power)

VSB3ONmin

tCP

(Internal)

32 KHz Domain

Internal

t32KVAL

PC8374T Datasheet(PDF) 32 Page - National Semiconductor (TI)

PC8374T Datasheet(HTML) 32 Page - National Semiconductor (TI)

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