PC8374T datasheet(13/48 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

Revision 1.1

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1.4.6

Keyboard and Mouse Controller (KBC)

1.4.7

General-Purpose I/O (GPIO)

Signal

Pin(s)

I/O Buffer Type Power Well

Description

KBCLK

I/O

INTS/OD14

VDD3

Keyboard Clock. Keyboard clock signal. External pull-up resistor

is required for PS/2 compliance. This pin is monitored during

VDD3 power-off for wake-up event detection.

KBDAT

I/O

INTS/OD14

VDD3

Keyboard Data. Keyboard data signal. External pull-up resistor is

required for PS/2 compliance. This pin is monitored during VDD3

power-off for wake-up event detection.

MCLK

I/O

INTS/OD14

VDD3

Mouse Clock. Mouse clock signal. External pull-up resistor is

required for PS/2 compliance. This pin is monitored during VDD3

power-off for wake-up event detection.

MDAT

I/O

INTS/OD14

VDD3

Mouse Data. Mouse data signal. External pull-up resistor is

required for PS/2 compliance. This pin is monitored during VDD3

power-off for wake-up event detection.

KBRST

7I/O

INT/OD8,

O4/8

VDD3

KBD Reset. Keyboard reset (P20) quasi-bidirectional output.

GA20

I/O

INT/OD8,

O4/8

VDD3

Gate A20. KBC gate A20 (P21) quasi-bidirectional output.

Signal

Pin(s)

I/O Buffer Type Power Well

Description

GPIOE00

103

I/O

INTS/

OD8, O4/8

VSB3

General-Purpose I/O Ports. Each pin is configured

independently as input or I/O, with or without static pull-up (and

some also with or without static pull-down) and with either open-

drain or push-pull output type. These pins have event detection

capability to generate a wake-up event or an interrupt.

Note: If GPIOE12 is configured (on pin 74) make sure

that the pin’s default function does not interfere with

the circuit connected to the GPIO. Failure to do so may

result in irreversible damage to the chip.

118

INTS/

OD12, O6/12

VDD3

GPIOE01-06 104-106,

108-109,

111

INTS/

OD8, O4/8

VSB3

119-121,

124,

126-127

VDD3

GPIOE07

112

INTS/

OD8, O4/8

VSB3

128

INTS/

OD12, O6/12

VDD3

GPIOE10-13 116, 114,

115, 113

INTS2/

OD6, O3/6

VSB3

GPIOE12-13 74-75

INTS/

OD8, O4/8

GPIOE14,

GPIOE16-17

101,

100, 80

GPIO15

INTS/

OD8, O4/8

General-Purpose I/O Port. This pin is configured

independently as input or I/O with or without static pull-up and

with either open-drain or push-pull output type.

GPO11

117

OD8, O4/8

General-Purpose Output Port. This pin is configured

independently as output, with or without static pull-up and with

either open-drain or push-pull output type.

GPO12-13

122, 125

VDD3

PC8374T Datasheet(PDF) 13 Page - National Semiconductor (TI)

PC8374T Datasheet(HTML) 13 Page - National Semiconductor (TI)

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