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PC8374T Datasheet(PDF) 28 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC8374T
Description  SafeKeeper Desktop Trustedl/O
PDF  48 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC8374T Datasheet(HTML) 28 Page - National Semiconductor (TI)

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2.0 Device Characteristics (Continued)
www.national.com
28
Revision 1.1
2.4
AC ELECTRICAL CHARACTERISTICS
2.4.1
AC Test Conditions
Figure 3. AC Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V ±10%
Notes:
1. VSUP is either VDD3 or VSB3, according to the pin power well.
2. CL = 50 pF for all output pins except the following pin groups:
− C
L = 100 pF for Serial Port 1 and 2 pins (see Section 1.4.2 on page 10), Parallel Port pins
(see Section 1.4.4 on page 11) and Floppy Disk Controller pins (see Section 1.4.5 on page 12).
− C
L = 40 pF for IDE_RSTDRV pin.
− C
L = 400 pF for SMBus pins (see “SMBus Voltage Translation and Isolation Timing” on page 44).
These values include both jig and oscilloscope capacitance.
3. S1 = Open
− for push-pull output pins.
S1 = VSUP
− for high impedance to active low and active low to high-impedance transition measurements.
S1 = GND
− for high impedance to active high and active high to high-impedance transition measurements.
RL = 1.0 KΩ− for all the pins
4. For the FDC open-drain interface pins, S1 = VDD3 and RL = 150Ω.
2.4.2
Reset Timing
VSB Power-Up Reset
Symbol Figure
Description
Reference Conditions
Min1
1. Not tested. Guaranteed by design.
Max1
tIRST
4
Internal Power-Up Reset
Time
VSB3 power-up to
end of internal reset
Ended by
32 KHz
Clock Domain
t32KW + t32KVAL
2 +
17 * tCP
2. t32KW + t32KVAL from VSB3 power-up to 32 KHz domain toggling; see “Low-Frequency Clock Timing” on page 32.
5
Ended by
PCI_RESET
tLRST
tLRST
5
PCI_RESET active time
VSB3 power-up to end of PCI_RESET
10 ms
tIPLV
5
Internal VsbStrap1 strap pull-
up resistor, valid time3
3. Active only during VSB3 Power-Up reset.
Before end of internal reset
tIRST
tEPLV
5
External VsbStrap1 strap pull-
down resistor, valid time
Before end of internal reset
tIRST
Device
Under
Test
0.1
µf
Input
Output
RL
CL
S1
Load Circuit
AC Testing Input, Output Waveform
VSUP
2.4
0.4
2.0
0.8
Test Points
2.0
0.8
(unless otherwise specified)



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