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PC8374T Datasheet(PDF) 15 Page - National Semiconductor (TI) |
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PC8374T Datasheet(HTML) 15 Page - National Semiconductor (TI) |
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15 / 48 page  1.0 Signal/Pin Connection and Description (Continued) Revision 1.1 15 www.national.com 1.4.11 Clocks 1.4.12 Glue Functions MDAT 2 I INTS VSB3 Mouse Data Wake-Up. Generates a wake-up event when a specific mouse action is detected. SIOPME 99 O OD8, O4/8 VSB3 Power Management Event (SCI). Active level indicates that a wake-up event occurred, causing the system to exit its current sleep state. This signal has programmable polarity (default is active low). SLP_S3, SLP_S5 85, 86 IINTS4 VSB3 Sleep States 3 to 5. Active (low) level indicates the system is in one of the sleep states S3 or S5. These signals are generated by an external ACPI controller. YLW_LED, GRN_LED 95, 94 OOD24 VSB3 Power LEDs. Yellow and green LED drivers. Each indicates the Main power status or blinks under software control. Signal Pin(s) I/O Buffer Type Power Well Description CLOCKI32 91 I INTS VSB3 Low-Frequency Clock Input. 32.768 KHz clock for the TPM timing. CLOCKI14 65 I INTS VDD3 High-Frequency Clock Input. 14.31818 MHz clock for the on- chip, 48 MHz Clock Generator (for the Legacy modules). Signal Pin(s) I/O Buffer Type Power Well Description REF5V 70 O AO VSB3 Main Highest Active Supply, Reference Output. Reference voltage equal to the highest voltage between VDD5 and VDD3. External pull-up resistor to VDD5 is required. REF5V_STBY 72 O AO VSB3 Standby Highest Active Supply, Reference Output. Reference voltage equal to the highest voltage between VSB5 and VSB3. External pull-up resistor to VSB5 is required. PS_ON 81 O OD6 VSB3 Main Power Supply On/Off Control. Active (low) level turns the main power supply (VDD) on. External pull-up resistor to VSB5 is required. PWRGD_PS 82 I INTS4 VSB3 Power Good Signal from the Power Supply. Active level indicates the Main power supply voltage is valid. PWRGD_3V 84 O O3/6 VSB3 Power Good Output. Active level indicates: Main supply voltage is valid and the system is in a higher than S3 sleep state. CPU_PRESENT 83 I INTS4 VSB3 CPU Present. Active (low) level indicates a processor is currently plugged in. BKFD_CUT 77 O OD6 VSB3 Backfeed-Cut Control. Power distribution control (when switching between main and standby regulators) for system transition into and out of the S3 sleep state. External pull-up resistor to VSB5 is required. LATCHED_BF_ CUT 79 O O14/14 VSB3 Latched Backfeed-Cut. Power distribution control (when switching between main and standby regulators) for system transition into and out of the S5 sleep state. VSB5 71 I AI VSB3 Standby 5V Power Supply. Used for Resume Reset generation (Range: 0-5.5V, Backdrive protected). RSMRST 92 O O3/6 VSB3 Resume Reset. Power-Up reset signal based on the VSB5 supply voltage. Signal Pin(s) I/O Buffer Type Power Well Description |
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