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PC8374T Datasheet(PDF) 35 Page - National Semiconductor (TI) |
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PC8374T Datasheet(HTML) 35 Page - National Semiconductor (TI) |
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35 / 48 page  2.0 Device Characteristics (Continued) Revision 1.1 35 www.national.com 2.4.5 FDC Timing FDC Write Data Timing tDRP, tICP, tWDW Values FDC Drive Control Timing Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 1. Not tested. Guaranteed by design. 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width1 See tDRP, tICP and tWDW values in table below Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6 x tCP 1 1. tCP is the clock period defined for CLOCKI in “Clock Timing” on page 31. 125 2 x tICP 250 ns 500 Kbps 2000 6 x tCP 1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP 1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP 1 250 2 x tICP 500 ns Symbol Parameter Min Max Unit tDST DIR Setup to STEP Active1 1. Not tested. Guaranteed by design. 6 µs tIW Index Pulse Width 100 ns tSTD DIR Hold from STEP Inactive tSTR ms tSTP STEP Active (Low) Pulse Width1 8 µs tSTR STEP Rate Time1 0.5 ms tHDS tHDH tWDW HDSEL WGATE WDATA |
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