PC8374T datasheet(3/48 Pages) NSC

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Features (Continued)

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Revision 1.1

Bus Interface

■ LPC Bus Interface

— Based on Intel’s LPC Interface Specification Revi-

sion 1.1, August 2002

— I/O, Memory and 8-bit Firmware Memory read and

write cycles, Firmware Memory writes may insert

wait cycles

— Up to four 8-bit DMA channels

— Serial IRQ (SERIRQ)

— Supports SuperI/O register memory and I/O mapping

■ Configuration Control

— PnP Configuration Register structure

— Compliant with PC01 Specification Revision 1.0,

1999-2000

— Base Address strap (BADDR) to setup the address

of the Index-Data register pair (defaults to 2Eh/2Fh)

❏

TPM Index-Data register pair Base Address set

by the TPM (defaults to 7Eh/7Fh) or via SuperI/O

Configuration registers

— Flexible resource allocation for all logical devices:

❏

Relocatable base address

❏

15 IRQ routing options to serial IRQ

❏

Up to four optional 8-bit DMA channels

— Configurable feature sets:

❏

VSB3-powered pin multiplexing

Legacy Modules

■ Serial Ports 1 and 2

— Software compatible with the NS16550A and NS16450

— Support shadow register for write-only bit monitoring

— Data rates up to 1.5 Mbaud

■ Serial Infrared Port (SIR)

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— HP-SIR

— ASK-IR option of SHARP-IR

— DASK-IR option of SHARP-IR

— Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

■ IEEE 1284-compliant Parallel Port

— ECP, with Level 2 (14 mA sink and source output

buffers)

— Software or hardware control

— Enhanced Parallel Port (EPP) compatible with EPP

1.7 and EPP 1.9

— Supports EPP as mode 4 of the Extended Control

— Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— Supports a demand DMA mode mechanism and a

DMA fairness mechanism for improved bus utilization

— Protection circuit that prevents damage to the

parallel port when a printer connected to it is pow-

ered up or is operated at high voltages (in both

cases, even if the PC8374T is in power-down state)

■ Floppy Disk Controller (FDC)

— Software compatible with the PC8477 (the PC8477

contains a superset of the FDC functions in the

µDP8473, NEC µPD765A/B and N82077 devices)

— Error-free handling of data overrun and underrun

— Programmable write protect

— Supports FM and MFM modes

— Supports Enhanced mode command for three-mode

Floppy Disk Drive (FDD)

— Perpendicular recording drive support for 2.88 MBytes

— Burst (16-byte FIFO) and Non-Burst modes

— Full support for IBM Tape Drive Register (TDR)

implementation of AT and PS/2 drive types

— High-performance digital separator

— Supports fast tape drives (2 Mbps) and standard

tape drives (1 Mbps, 500 Kbps and 250 Kbps)

■ Keyboard and Mouse Controller (KBC)

— 8-bit

microcontroller,

software

compatible

with

8042AH and PC87911

— Standard interface (60h, 64h, IRQ1 and IRQ12)

— Supports two external swapable PS/2 interfaces for

keyboard and mouse

— Programmable, dedicated quasi-bidirectional I/O

lines (GA20/P21, KBRST/P20)

Power Management

■ Supports ACPI Specification Revision 2.0b, July 27, 2000

■ System Wake-Up Control (SWC)

— Optional

routing

events

generate

SCI

(SIOPME) on detection of:

❏

Keyboard or Mouse events

❏

Ring Indication RI on each of the two serial ports

❏

General-Purpose Input Events from 15 GPIO pins

❏

IRQs of the Keyboard and Mouse Controller

❏

IRQs of the other internal modules

— Optional routing of the SCI (SIOPME) to generate

IRQ (SERIRQ)

— Implements the GPE1_BLK of the ACPI General Pur-

pose (Generic) Register blocks with “child” events

— VSB3-powered event detection and event-logic con-

figuration

■ Enhanced Power Management (PM), including:

— Special configuration registers for power down

— Low-leakage pins

— Low-power CMOS technology

— Ability to disable all modules

— High-current LED drivers control (two LEDs) for

power status indication with:

❏

Standard blinking, controlled by software

❏

Advanced blinking, controlled by power supply

status, sleep state or software

❏

Special blinking, controlled by power supply

status, sleep state and software bit

— VBAT-powered indication of the Main power supply

state before an AC power failure

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