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D17133CS Datasheet(PDF) 172 Page - NEC |
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D17133CS Datasheet(HTML) 172 Page - NEC |
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172 / 289 page  CHAPTER 14 INTERRUPT FUNCTIONS 157 Figure 14-4. Interrupt Acceptance Timing Chart (INTE=1 and IP ×××=1) (3/3) <8> When an interrupt has occurred during skipping (NOP handling) by a skip instruction Remarks 1. The INT cycle is for preparing interrupts. During this cycle, PC and PSWORD saving and IRQ clearing are performed. 2. For execution of the MOVT instruction, two instruction cycles are exceptionally required. 3. The EI instruction is considered to prevent multiple interrupts from occurring when returning from the interrupt operation. Machine cycle Instruction IRQ ××× M0 Skip instruction INT cycle M1 M2 M3 M0 M1 M2 M3 M0 M1 M2 M3 M0 M1 Vector address instruction Interrupt occurrence recognized Handled as NOP |
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