D17133CS datasheet(170/289 Pages) NEC

170 / 289 page

CHAPTER 14

INTERRUPT FUNCTIONS

155

14.3.3 Interrupt Acceptance Timing

Figure 14-4 shows the interrupt acceptance timing chart. The

µPD17120 subseries executes an instruction with

16 clocks, which is one instruction cycle. One instruction cycle is subdivided into M0-M3 in terms of 4 clocks as

a unit.

The timing of the program recognizing the interrupt occurrence coincides with the edge preceding the M2.

Figure 14-4. Interrupt Acceptance Timing Chart (when INTE=1 and IP

×××=1) (1/3)

<1> When an interrupt has occurred before M2 of an instruction other than MOVT or EI

Machine cycle

Instruction

IRQ

×××

An instruction other than MOVT or EI

INT cycle

Vector address instruction

Interrupt occurrence recognized

<2> When the skip condition for the skip instruction is materialized in <1>

<3> When an interrupt has occurred after M2 of an instruction other than MOVT or EI

Machine cycle

Instruction

IRQ

×××

INT cycle

Vector address

instruction

Interrupt occurrence recognized

An instruction other than MOVT or EI An instruction other than MOVT or EI

Machine cycle

Instruction

IRQ

×××

Skip instruction

Handled as NOP

INT cycle

Interrupt occurrence recognized

Vector address

instruction

D17133CS Datasheet(PDF) 170 Page - NEC