NTP53X2 datasheet(105/133 Pages) NXP

105 / 133 page

NXP Semiconductors

NTP53x2

NTAG 5 link - NFC Forum-compliant I2C bridge

NTP53x2

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Product data sheet

Rev. 3.3 — 3 July 2020

COMPANY PUBLIC

544533

105 / 133

PWMx_ON and PWMx_OFF defines the starting point and end point of the PWMx output

is asserted to HIGH.

To calculate proper PWMx_ON (start of HIGH level) and PWMx_OFF (end of HIGH level)

values, PWMx_RESOLUTION_CONF value and PWM_PRESCALE values need to be

set to achieve desired PWM frequency. As an example 12-bit resolution is chosen. Duty

cycle shall be set to 20 % and start time shall be 10 % offset.

Start Time 10 %: 212 * 10/100= 4096 * 10/100 = ~410 -> PWMx_ON = 19Ah

PWM Duty Cycle 20 %: 212 * 20/100= 4096 * 20/100 = ~819 -> PWMx_OFF = 410 + 819

= 1229 = 4CDh

aaa-035480

819

410

1229

PWM_ON

PWM_OFF

819

4095

410

1229

Figure 12. Pulse Width Modulation Example

How to use PWM in applications is described in AN11203.

8.3.5 Standby mode

To minimize overall current consumption, when the IC is supplied via VCC NTAG 5 link

can be set to standby mode by writing related session bit form NFC or I2C perspective.

The IC will leave standby mode according to configuration when NFC field is detected,

automatically, or HPD pin gets pulled to HIGH for at least 20 µs and released again. In

standby mode the current is typically less than 6 µA.

Worst case standby current consumption values can be found in Section 10.1 table.

In case SDA/SCLGPIO/PWM pins are not used the pins can be left floating. However, to

ensure lowest standby current, following settings are needed:

CONFIG bytes USE_CASE_CONF shall be set in any case to GPIO/PWM, both pins

SDA_GPIO1 and SCL_GPIO0 shall be set as input using weak pull-up (GPIOx_IN in).

Block 37h: CONFIG_1, USE_CASE_CONF shall be set to GPIO/PWM (10b) and

CONFIG, GPIOx_IN, both shall be set to plain input with weak pullup (01b).

Block 39h: PWM_GPIO_CONFIG_0, SDA_GPIO1 and SCL_GPIO0 shall both be set to

1b to define them as general-purpose input.

8.3.6 Hard power-down mode

In hard power-down mode NTAG 5 link is switched off using hard power down pin. When

pulled to HIGH, the hard power down current is typically less than 0.25 µA. This mode

can only be left by connecting HPD pin to ground.

There is no hard power-down mode, when using SO8 packaged version of NTAG 5 link.

Worst case hard power down current consumption values can be found in Section 10.1

table.

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