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NTP53X2 Datasheet(PDF) 127 Page - NXP Semiconductors

Part # NTP53X2
Description  NTAG 5 link - NFC Forum-compliant I2C bridge
PDF  133 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

NTP53X2 Datasheet(HTML) 127 Page - NXP Semiconductors

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NXP Semiconductors
NTP53x2
NTAG 5 link - NFC Forum-compliant I2C bridge
NTP53x2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.3 — 3 July 2020
COMPANY PUBLIC
544533
127 / 133
Tables
Tab. 1.
Ordering information ..........................................6
Tab. 2.
Marking codes ...................................................7
Tab. 3.
Pin description for XQFN16 .............................. 9
Tab. 4.
Pin description for TSSOP16 .......................... 10
Tab. 5.
Pin description for SO8 ...................................11
Tab. 6.
User memory organization .............................. 13
Tab. 7.
Memory content at delivery .............................13
Tab. 8.
COUNTER BLOCK data structure .................. 14
Tab. 9.
Preset counter data structure ..........................14
Tab. 10. Increment counter data structure .................... 15
Tab. 11. Configuration Memory organization .................15
Tab. 12. 32 Byte Originality Signature ...........................20
Tab. 13. Configuration Header (CH) location ................ 20
Tab. 14. Configuration Header Codes ...........................20
Tab. 15. Customer ID (CID) location .............................21
Tab. 16. NFC Global Crypto Header (GCH) location .....22
Tab. 17. Global Crypto Header Configuration in plain
password mode ...............................................22
Tab. 18. Global Crypto Header Configuration Value
in AES mode ...................................................22
Tab. 19. Crypto Configuration Header (CCH) location ...23
Tab. 20. Crypto Configuration Header Values ...............23
Tab. 21. NFC Authentication Limit Counter (NFC_
AUTH_LIMIT) location .....................................24
Tab. 22. NFC Key Header (KHx) location ..................... 25
Tab. 23. NFC Key Header Values .................................25
Tab. 24. NFC Key Privileges (KPx) location ..................26
Tab. 25. Definition of NFC Key Privileges bytes KPx .... 26
Tab. 26. Key location .....................................................27
Tab. 27. Plain Password location ..................................27
Tab. 28. I2C Password location .................................... 28
Tab. 29. I2C Key Authenticate Password location .........28
Tab. 30. I2C Key Header (I2C_KH) location ................. 29
Tab. 31. I2C Key Header Values .................................. 29
Tab. 32. I2C Protection Pointer and Configuration
location ............................................................ 29
Tab. 33. I2C Memory organization example ..................30
Tab. 34. I2C Protection Pointer Configuration (I2C_
PPC) ................................................................30
Tab. 35. I2C Authentication Limit Counter (I2C_
AUTH_LIMIT) location .....................................31
Tab. 36. Configuration Bytes Location (CONFIG) ......... 31
Tab. 37. Configuration Definition (CONFIG_0) ..............32
Tab. 38. Configuration Definition (CONFIG_1) ..............32
Tab. 39. Configuration Definition (CONFIG_2) ..............33
Tab. 40. Synchronization Block Bytes Location
(SYNCH_DATA_BLOCK) ................................33
Tab. 41. Synchronization Block Register Bytes
Location (SYNCH_DATA_BLOCK_REG) ........33
Tab. 42. PWM and GPIO Configuration Location
(PWM_GPIO_CONFIG) .................................. 34
Tab. 43. PWM and GPIO Configuration Definition
(PWM_GPIO_CONFIG_0) .............................. 34
Tab. 44. PWM and GPIO Configuration Definition
(PWM_GPIO_CONFIG_1
and
PWM_
GPIO_CONFIG_1_REG) .................................34
Tab. 45. Pulse Width Modulation Duty Cycle
Configuration Location (PWMx_ON and
PWMx_OFF) ....................................................35
Tab. 46. Pulse Width Modulation Duty Cycle Session
Register Location (PWMx_ON and PWMx_
OFF) ................................................................ 35
Tab. 47. Pulse
Width
Modulatin
ON
time
Configuration Definition (PWMx_ON and
PWMx_ON_REG) ............................................35
Tab. 48. Pulse
Width
Modulation
OFF
time
Configuration Definition (PWMx_OFF and
PWMx_OFF_REG) ..........................................35
Tab. 49. Watch Dog Timer Configuration Location
(WDT_CONFIG) .............................................. 36
Tab. 50. Watch Dog Timer Configuration Register
Location (WDT_CONFIG_REG) ......................36
Tab. 51. Watch Dog Timer Enable Definition (WDT_
ENABLE and WDT_EN_REG) ........................ 36
Tab. 52. Energy harvesting Configuration Location
(EH_CONFIG) ................................................. 36
Tab. 53. Energy harvesting Configuration Value
Definition (EH_CONFIG) ................................. 36
Tab. 54. Event Detection Configuration Location
(ED_CONFIG) ................................................. 37
Tab. 55. Event Detection Configuration Register
Location (ED_CONFIG_REG) .........................37
Tab. 56. Event Detection Definition (ED_CONFIG
and ED_CONFIG_REG) ................................. 37
Tab. 57. Event Detection Clear Register Location
(ED_INTR_CLEAR_REG) ............................... 39
Tab. 58. Event Detection Clear Register (ED_INTR_
CLEAR_REG) ..................................................39
Tab. 59. I2C Slave Configuration Location ....................39
Tab. 60. I2C Slave Configuration Definition (I2C_
SLAVE_ADDR) ................................................39
Tab. 61. I2C Slave Configuration Definition (I2C_
SLAVE_CONFIG) ............................................39
Tab. 62. I2C Master Clock Settings Configuration
Location (I2C_MASTER_CONFIG) ................. 40
Tab. 63. I2C Master Clock Configuration Definition
(I2C_MASTER_SCL_LOW) ............................ 40
Tab. 64. I2C Master Clock Configuration Definition
(I2C_MASTER_SCL_HIGH) ............................40
Tab. 65. Device Security Configuration Byte location ....40
Tab. 66. Device Security Byte Definition (DEV_SEC_
CONFIG) ......................................................... 40
Tab. 67. SRAM and Configuration Byte location ........... 41
Tab. 68. SRAM
and
Configuration
Protection
(SRAM_CONF_PROT) ....................................41
Tab. 69. Restricted AREA_1 Pointer location ................42
Tab. 70. Memory organization example from NFC
perspective ...................................................... 42
Tab. 71. Application Family Identifier (AFI) location ...... 42
Tab. 72. Data Storage Format Identifier (DSFID)
location ............................................................ 43



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