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NTP53X2 Datasheet(PDF) 132 Page - NXP Semiconductors |
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NTP53X2 Datasheet(HTML) 132 Page - NXP Semiconductors |
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132 / 133 page ![]() NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 132 / 133 Contents 1 General description ............................................ 1 2 Features and benefits .........................................3 3 Applications .........................................................5 4 Ordering information .......................................... 6 5 Marking .................................................................7 6 Block diagram ..................................................... 8 7 Pinning information ............................................ 9 8 Functional description ......................................12 8.1 Memory Organization ...................................... 12 8.1.1 General ............................................................ 12 8.1.2 User memory ................................................... 12 8.1.2.1 16-bit counter ...................................................13 8.1.3 Configuration memory ..................................... 15 8.1.3.1 Originality Signature ........................................ 20 8.1.3.2 Configuration Header .......................................20 8.1.3.3 Customer ID (CID) ...........................................21 8.1.3.4 NFC Global Crypto Header ............................. 21 8.1.3.5 NFC Crypto Configuration Header ...................23 8.1.3.6 NFC Authentication Limit Counter ................... 23 8.1.3.7 NFC Key Header ............................................. 24 8.1.3.8 NFC Key Privileges ......................................... 25 8.1.3.9 Keys and passwords ....................................... 26 8.1.3.10 I2C Key Header ...............................................28 8.1.3.11 I2C Protection Pointer and Condition .............. 29 8.1.3.12 I2C Authentication Limit Counter .....................31 8.1.3.13 Configuration ....................................................31 8.1.3.14 Synchronization Block ..................................... 33 8.1.3.15 Pulse Width Modulation and GPIO configuration .................................................... 33 8.1.3.16 Pulse Width Modulation duty cycle settings .....35 8.1.3.17 Watch Dog Timer settings ............................... 35 8.1.3.18 Energy harvesting settings .............................. 36 8.1.3.19 Event detection pin configuration settings ....... 37 8.1.3.20 I2C slave configuration settings .......................39 8.1.3.21 I2C master clock configuration settings ........... 39 8.1.3.22 Device security configuration bytes ................. 40 8.1.3.23 SRAM and Configuration protection ................ 41 8.1.3.24 Restricted AREA_1 pointer ..............................41 8.1.3.25 Application Family Identifier .............................42 8.1.3.26 Data Storage Format Identifier ........................ 43 8.1.3.27 Electronic Article Surveillance ID .....................43 8.1.3.28 NFC protection pointer .................................... 43 8.1.3.29 NFC Protection Pointer Conditions ..................44 8.1.3.30 NFC lock bytes ................................................44 8.1.3.31 I2C lock bytes ..................................................45 8.1.3.32 Device configuration section lock bytes ...........45 8.1.4 Session registers ............................................. 48 8.1.4.1 Status register ................................................. 49 8.1.4.2 Configuration register ...................................... 51 8.1.4.3 Synchronization block register .........................53 8.1.4.4 Pulse Width Modulation and GPIO configuration register ....................................... 53 8.1.4.5 Pulse Width Modulation duty cycle register ..... 54 8.1.4.6 Watch Dog Timer register ............................... 54 8.1.4.7 Energy harvesting register ...............................54 8.1.4.8 Event detection register ...................................55 8.1.4.9 I2C slave register settings ............................... 55 8.1.4.10 System reset generation ..................................56 8.1.4.11 Clear event detection register ..........................56 8.1.4.12 I2C master status registers ..............................57 8.1.5 SRAM ...............................................................58 8.2 NFC interface .................................................. 60 8.2.1 Passive communication mode .........................60 8.2.2 State diagram and state transitions ................. 60 8.2.2.1 POWER-OFF state ..........................................61 8.2.2.2 READY state ................................................... 61 8.2.2.3 SELECTED state .............................................62 8.2.2.4 SELECTED SECURE state .............................62 8.2.2.5 QUIET state .....................................................63 8.2.3 Command set .................................................. 63 8.2.3.1 Commands for state transitions .......................65 8.2.3.2 Configuration operations ..................................66 8.2.3.3 PWD Authentication .........................................67 8.2.3.4 AES Authentication ..........................................76 8.2.3.5 Memory operations ..........................................80 8.2.3.6 SRAM operations .............................................85 8.2.3.7 Originality Signature ........................................ 86 8.2.3.8 I2C Transparent Channel ................................ 87 8.2.3.9 Other ................................................................90 8.2.4 Data integrity ................................................... 98 8.2.5 Error Handling ................................................. 98 8.2.5.1 Transmission Errors .........................................98 8.2.5.2 Not supported commands or options ...............98 8.3 Wired Interface ................................................ 99 8.3.1 I2C interface .................................................... 99 8.3.1.1 Slave mode ......................................................99 8.3.1.2 Master mode of NTP5332 ............................. 101 8.3.1.3 Watch Dog Timer .......................................... 101 8.3.1.4 Command Set ................................................102 8.3.1.5 Error Handling ............................................... 103 8.3.2 Event detection ..............................................103 8.3.3 GPIO ..............................................................104 8.3.4 PWM .............................................................. 104 8.3.5 Standby mode ............................................... 105 8.3.6 Hard power-down mode ................................ 105 8.4 Arbitration between NFC and I2C interface ....106 8.4.1 NFC Mode ..................................................... 106 8.4.2 I2C Mode .......................................................106 8.4.3 Normal Mode ................................................. 106 8.4.4 SRAM Mirror Mode ........................................106 8.4.5 SRAM Pass-Through Mode ...........................106 8.4.6 SRAM PHDC Mode .......................................107 8.5 Energy harvesting ..........................................107 8.6 Security ..........................................................108 8.6.1 Locking EEPROM to read only ......................108 8.6.2 Memory Areas ............................................... 109 8.6.3 Plain password authentication ....................... 110 8.6.4 AES authentication ........................................ 110 8.7 NFC privacy mode .........................................111 8.8 Programmable Originality signature ...............111 9 Limiting values ................................................113 10 Characteristics ................................................ 114 |
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