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W6100 Datasheet(PDF) 142 Page - WIZnet Co., Ltd |
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W6100 Datasheet(HTML) 142 Page - WIZnet Co., Ltd |
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142 / 149 page  W6100 – Hardwired Dual TCP/IP Stack Controller 142/149 8.4 AC Characteristics 8.4.1 Reset Timing Figure 39 Reset Timing Table 18 Reset Table Symbol Description Min Typ Max TRST Reset Time 350 ns 580 ns 1.0 us TSTA Stable Time - 60.3 ms TFL Fast to Low Time by MR2[CLKSEL] 100 ns - Fast to Low Time by PHYCR1[RST] or PHYCR1[PWDN] 300 ns TPRST PHY Auto Reset Time 0.6 ms - PHY Power Down Time 200 us Clock Switch Time 200 ns TLF Low to Fast Time by MR2[CLKSEL] 100 ns - Low to Fast Time by PHYCR1[RST] or PHYCR1[PWDN] 100 ns *COMMENT: PHY power-down mode has TFI and TLF (In PHY power-down mode, SYS_CLK switches to low clock. After TFL , users can disable PHY power-down mode. *CAUTION: Users must not set PHY auto reset and PHY power-down mode at the same time. |
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