RX113 datasheet(120/131 Pages) RENESAS

120 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 120 of 131

Sep 07, 2020

RX113 Group

5. Electrical Characteristics

5.13

ROM (Flash Memory for Code Storage) Characteristics

Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/

erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is

performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is

counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is

prohibited).

Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.

Note 3. This result is obtained from reliability testing.

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

Note:

The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.

Table 5.60

ROM (Flash Memory for Code Storage) Characteristics (1)

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Reprogramming/erasure cycle*1

NPEC

1000

—

Times

Data hold time

After 1000 times of NPEC

tDRP

20*2, *3

—

Year

Ta = +85°C

Table 5.61

ROM (Flash Memory for Code Storage) Characteristics (2)

High-speed operating mode Conditions: 2.7 V

≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V

Temperature range for the programming/erasure operation: Ta = –40 to +105°C

Item

Symbol

FCLK = 1 MHz

FCLK = 32 MHz

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Programming time

4-byte

tP4

—

103

931

—

489

µs

Erasure time

1-Kbyte

tE1K

—

8.23

267

—

5.48

214

256-Kbyte

tE256K

—

407

925

—

457

Blank check time

4-byte

tBC4

—

15.9

µs

1-Kbyte

tBC1K

—

1.58

—

0.127

Erase operation forcible stop time

tSED

—

21.6

—

12.8

µs

Start-up area switching setting time

tSAS

—

12.6

543

—

6.16

432

Access window time

tAWS

—

12.6

543

—

6.16

432

ROM mode transition wait time 1

tDIS

2—

—2—

—

µs

ROM mode transition wait time 2

tMS

5—

—5—

—

µs

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