LT8697 datasheet(15/40 Pages) AD

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LT8698S/LT8698S-1

Rev. A

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OPERATION

The LT8698S is a highly efficient synchronous, monolithic

USB charger with cable drop compensation and robust USB

dataline protection. As such, the LT8698S includes a switch-

ing regulator optimized for powering the 5V USB VBUS rail

and two analog switches that tie to the high speed USB 2.0

datalines to provide fault and ESD protection to the upstream

USB host IC. Finally, the LT8698S includes many USB charger

profiles to allow high current charging of portable devices.

The LT8698S regulator is a monolithic, constant frequency,

peak current mode step-down DC/DC converter. An oscillator,

with frequency set using a resistor on the RT pin, turns on the

internal top power switch at the beginning of each clock cycle.

Current in the inductor then increases until the top switch

current comparator trips and turns off the top power switch.

The peak inductor current at which the top switch turns off is

controlled by the voltage on the VC node. The error amplifier

compares the output voltage on the USB5V pin through an

internal resistor divider to an internal reference and servos

the VC node to regulate the USB5V pin to 5V. When the load

current increases it causes a reduction in the feedback voltage

relative to the reference leading the error amplifier to raise

the VC voltage until average inductor current matches the

new load current. When the top power switch turns off, the

synchronous bottom power switch turns on until the next

clock cycle begins or inductor current falls to zero when not

in forced continuous mode. If overload conditions result in a

current higher than the bottom switch current limit flowing

in the bottom switch, the next clock cycle will be delayed

until switcher current returns to a safe level. In addition, dur-

ing a fault condition in which USB5V is shorted to ground,

the BUS/ISN voltage is regulated to 6.05V to limit the output

voltage to a safe level for connected devices. Finally, during

an output fault condition, the LT8698S provides an accurate,

average output current limit using an external sense resistor

connected across the OUT/ISP and BUS/ISN pins.

The LT8698S includes cable drop compensation to provide

5V regulation of the VBUS rail at the end of a long, resistive

cable even with high load current. To implement cable

drop compensation, the LT8698S drives the RCBL pin to

46 • (VOUT/ISP - VBUS/ISN). Current sourced from the RCBL

pin through the RCBL resistor is derived from the USB5V

pin, creating an output offset across the RCDC resistor

above the 5V USB5V pin voltage that is proportional to

the RCDC/RCBL resistor ratio.

The “S” in the LT8698S part name refers to the second

generation Silent Switcher Technology. This technology

allows fast switching edges for high switching regulator

efficiency at high switching frequency, while simultane-

ously achieving good EMI performance. This technology

includes the integration of ceramic capacitors into the

package for the VIN, INTVCC and BST (C1 to C4 in the

Block Diagram). These capacitors keep all of the AC cur-

rent loops small which improves EMI performance. The

LT8698S-1 does not include integrated ceramic capaci-

tors tied to VIN.

An EN/UV pin voltage above 1.46V enables the switch-

ing regulator, dataline switches and associated circuitry.

An EN/UV pin voltage below 1.31V stops switching and

opens the dataline switches. EN/UV pin voltage below

0.25V reduces VIN current to <1µA.

The LT8698S operates primarily in forced continuous

mode (FCM) for fast transient response and full frequency

operation over a wide load range. To improve regulator

efficiency at light load, the LT8698S can operate in pulse-

skip mode (PSK). PSK reduces the switching frequency

at light load current and reduces VIN quiescent current

between pulses. Ground the SYNC/MODE pin for PSK

operation, float it for FCM operation or apply a DC voltage

higher than 3.2V to use FCM with spread spectrum modu-

lation (SSM). If a clock is applied to the SYNC/MODE pin,

the internal oscillator will synchronize to the external clock

frequency and operate in FCM. While in FCM the oscilla-

tor operates continuously and rising SW transitions are

aligned to the clock. During light loads, the inductor cur-

rent is allowed to go negative to maintain the programmed

switching frequency. The LT8698S can sink current from

the output, improving the load step response. Minimum

current limits for both power switches are enforced to

prevent large negative inductor current from flowing back

into the input. SSM dithers the switching frequency from

the programmed value set by the RT pin up to 20% higher

than the programmed value to spread out the switching

energy in the frequency domain.

Comparators monitoring the USB5V pin voltage will pull

the FLT pin low if the output voltage varies more than

±7% (typical) from the set point, or if a power supply fault

condition is present.

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