LT8697 datasheet(29/40 Pages) AD

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LT8698S/LT8698S-1

Rev. A

For more information www.analog.com

(b) 20V Fault on HD+

(a) CLAMP Circuit to Reduce Overshoot

APPLICATIONS INFORMATION

CDP connection in progress. While the STATUS pin oscil-

lates, the select pins are locked out from changing the

LT8698S state.

The device will then remove the voltage source from D+

and the current source from D– and place a 100µA cur-

rent source on D+ and a 0.6V voltage source on D– for

40ms. The LT8698S will respond by removing the 0.6V

voltage source from D–. The LT8698S will monitor D– to

see if the 0.6V voltage source is present for 40ms. This

is secondary detection, and it indicates that the host port

is CDP capable. The STATUS pin will continue to oscillate

and the select pins will continue to be locked out.

The device can now charge from VBUS at up to 1.5A and

proceed to enumerate, pulling either D+ or D– above logic

high to initiate a USB connection and to indicate the speed

of the connection. When either D+ or D– is pulled above

logic high, the LT8698S will remove the 100µA current

source from D+ and the STATUS pin will stop oscillating

and stay high, indicating that the CDP sequence is done.

When STATUS is not oscillating, the select pins are no

longer locked out.

This enumeration must occur within 1s of the initial attach

when D+ is pulled to 0.6V or the LT8698S will stop the

CDP handshake and return to the initial CDP state, wait-

ing for a connection. If the device pulls D+ or D– above

logic high during the CDP sequence before the sequence

is completed, the LT8698S will interpret that the device is

not CDP capable, will stop the CDP sequence, and indicate

that the CDP handshake failed.

D+ or D– pulled above logic high will end the CDP hand-

shake sequence. To restart CDP, the select pins must input

any state other than select state 0, 1, or 2 and then be

returned to the desired CDP input state.

Select state 2 allows the user to query if the CDP hand-

shake sequence was successful or not. It is intended to

be used after a portable device connects during select state

0 or 1. It does not affect the datalines, but after a con-

nection, the STATUS pin will indicate if a successful CDP

sequence was completed. While select state 2 is selected,

STATUS high indicates a successful CDP connection, and

STATUS low indicates an unsuccessful CDP connection.

If select 2 is selected with neither select 0 nor 1 states

1s/DIV

IHD+

1A/DIV

ILD+

0.5A/DIV

8698S F12b

20V FAULT APPLIED TO

HD+ THROUGH 3m AWG

24 TWISTED PAIR CABLE

LD+ 50 TO GND

HD+

10V/DIV

CLAMP

10V/DIV

CLAMP

CCLMP

0.1F

DCLMP

DFLT22A

8698S F12a

interfere with the LT8698S CDP sequence. Select state

0 keeps the dataline switches closed. Select state 1 per-

forms the CDP sequence with the dataline switches open

and 20k termination resistors tied from HD+ and HD– to

GND. Select state 1 allows the LT8698S to handle the CDP

sequence independently of the host µController and only

connects the dataline switches after the CDP sequence

is complete or the portable device attempts a connection

without CDP. In select state 1, after the CDP sequence

is complete, the internal 20k termination resistors are

removed from the datalines and the dataline switches

are closed.

When CDP is selected with either select 0 or select 1

states, the LT8698S connects a 100µA current source to

D+, asserts STATUS low and waits for a device to attach to

the USB socket. Once a device is attached, a CDP compli-

ant device will place a 0.6V voltage source on D+ and a

100µA current source on D– for 40ms. The LT8698S will

recognize 0.6V on D+ and will apply a 0.6V voltage source

to D– within 20ms. This is CDP primary detection, and

it indicates that the host port is either CDP or dedicated

charger Port (DCP) capable. The LT8698S will also start

to oscillate the STATUS pin with a 9ms period to indicate a

Figure 12. Cable Faults

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