LT8697 datasheet(16/40 Pages) AD

16 / 40 page

LT8698S/LT8698S-1

Rev. A

For more information www.analog.com

Dataline analog switches allow connection and disconnec-

tion between the HD+ pin and the LD+ pin and between the

HD– pin and the LD– pin. When connected, the switches

provide low resistance over the full 0V to 3.6V common

mode range and can block 0V to 20V on the HD+/– side

and 6V on the LD+/– side. High speed circuitry discon-

nects the switches in the event of a fault or ESD on the

HD+/– side.

The LT8698S includes many charger profiles including

USB BC 1.2 CDP, DCP, and SDP as well as common pro-

prietary profiles. Each profile ties various components

to the datalines. This could be resistive dividers, a short

between the datalines, or voltage sources and current

sources. These profiles might be passive or could react

OPERATION

to the device plugged into the USB socket in some active

manner. The profile allows the device plugged into the

USB socket to identify a high current charger and draw

more current from VBUS than the 0.5A that would usually

be allowed from a standard USB 2.0 socket.

SEL1-3 pins are tristate inputs that allow the host

µController to control the behavior of the LT8698S.

Internal resistive dividers bias these pins to 1V when a

high Z input is applied. The SEL1-3 pins are de-bounced

for 1.5ms prior to allowing a state change to the LT8698S.

The STATUS pin is an open drain output whose function is

determined by the state selected by the SEL1-3 pins. This

pin can output high or low or oscillate with a 9ms period.

Cable Drop Compensation

The LT8698S includes the necessary circuitry to imple-

ment cable drop compensation. Cable drop compensa-

tion allows the regulator to maintain 5V regulation on the

USB VBUS rail despite high cable resistance. The LT8698S

increases its local output voltage (VBUS/ISN) above 5V as

the load increases to keep VBUS regulated to 5V. This

compensation does not require running an additional pair

of Kelvin sense wires from the regulator to the load, but

does require the system designer to know the cable resis-

tance RCABLE as the LT8698S does not sense this value.

Program the cable drop compensation using the ratio of

Equation 1.

RCBL =46•

RSEN •RCDC

RCABLE

⎛

⎝

⎜

⎞

⎠

⎟

(1)

where RCDC is a resistor tied between the regulator out-

put and the USB5V pin, RCBL is a resistor tied between

the RCBL pin and GND, RSEN is the sense resistor tied

between the OUT/ISP and BUS/ISN pins in series between

the regulator output and the load, and RCABLE is the

cable resistance. RSEN must be 10mΩ for 2.4A applica-

tions and 8mΩ for 3A applications for the LT8698S to

function properly.

APPLICATIONS INFORMATION

The current flowing into the USB5V pin through RCDC is iden-

tical to the current flowing through RCBL. While the ratio of

these two resistors should be chosen per the equation above,

choose the absolute values of these resistors to keep this

current between 30µA and 1200µA at full load current. This

restriction results in RCBL and RCDC values between 1k and

40.2k. If IUSB5V is too low, capacitive loading on the RCBL

pin will degrade the load step transient performance of the

regulator. If IUSB5V istoohigh,theRCBL pinwillgointocurrent

limit and the cable drop compensation feature will not work.

Capacitance across the remote load to ground downstream

of RSEN forms a left half plane zero in the LT8698S device's

feedback loop due to cable drop compensation. CBUS and the

input capacitance of a portable device tied to the USB socket

typically form this zero. CCDC reducesthecabledropcompen-

sation gain at high frequency. The 4.7nF CCDC capacitor tied

across the 2k RCDC is required for stability of the LT8698S’s

output. If RCDC is changed, CCDC should also be changed

to maintain roughly the same 10µs RC time constant. If the

capacitance across the remote load is large compared to the

LT8698S output capacitors COUT and CBUS, a longer RCDC •

CCDC time constant may be necessary for stability depending

on the amount of cable drop compensation used. Output sta-

bility should always be verified in the end application circuit.

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