PCM1820 datasheet(60/130 Pages) TI

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8.5 Programming

The device contains configuration registers and programmable coefficients that can be set to the desired values

for a specific system and application use. These registers are called device control registers and are each eight

bits in width, mapped using a page scheme.

Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which

is the default page setting at power up and after a software reset. All programmable coefficient registers are

located in page 2, page 3, and page 4. The current page of the device can be switched to a new desired page by

using the PAGE[7:0] bits located in register 0 of every page.

8.5.1 Control Serial Interfaces

The device control registers can be accessed using I2C communication to the device. The device operates with

a fixed I2C address and can be configured using this address.

8.5.1.1 I2C Control Interface

The device supports the I2C control protocol as a slave device, and is capable of operating in standard mode,

fast mode, and fast mode plus. The I2C control protocol requires a 7-bit slave address. The 7-bit slave address

is fixed at 1001110 and cannot be changed. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the

I2C slave address is fixed to 1001100 in order to allow simultaneous I2C broadcast communication to multiple

devices in the system, including the TLV320ADCx140, PCMD3140, and PCMD3180 devices. Table 8-53 lists the

possible device addresses resulting from this configuration.

Table 8-53. I2C Slave Address Settings

I2C_BRDCAST_EN (P0_R2_D2)

I2C SLAVE ADDRESS

0 (default)

1001 110

1001 100

8.5.1.1.1 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits

in a system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In

addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.

Each transfer operation begins with the master device driving a start condition on the bus and ends with the

master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the

clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and

a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock

period.

The master device drives a start condition followed by the 7-bit slave address and the read/write (R/W) bit to

open communication with another device and then waits for an acknowledgment condition. The slave device

holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master

device transmits the next byte of the sequence. Each slave device is addressed by a unique 7-bit slave

address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a

wired-AND connection.

TLV320ADC6120

SBASA92A – DECEMBER 2020 – REVISED JUNE 2021

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